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| Search found 6 matches |
| Author | Message |
|---|---|
 Topic: HW SPI clocking 12 bits between SS... Can it be done? |
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| Andrei S Replies: 14 Views: 24358 |
 Forum: General CCS C Discussion Posted: Wed Aug 13, 2014 11:07 am Subject: HW SPI clocking 12 bits between SS... Can it be done? |
| Holly smokes, in a dark corner of the FPGA board there is a jumper that controls the output SPI timing. Format still bad, but I can slow it down to the point that SS drops and the first clock is abou ... | |
| Topic: HW SPI clocking 12 bits between SS... Can it be done? |
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| Andrei S Replies: 14 Views: 24358 |
Forum: General CCS C Discussion Posted: Tue Aug 12, 2014 1:56 pm Subject: HW SPI clocking 12 bits between SS... Can it be done? |
| SS drops and the rising edge of the clock comes in about 275ns later. I will then sample data on falling clock, just 250 ns after that.
Can I attach an image (scope screenshot) without hosting it ... |
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| Topic: HW SPI clocking 12 bits between SS... Can it be done? |
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| Andrei S Replies: 14 Views: 24358 |
Forum: General CCS C Discussion Posted: Tue Aug 12, 2014 12:29 pm Subject: HW SPI clocking 12 bits between SS... Can it be done? |
| Huh, won't rely on the email notification of new post I guess... Anyway, sorry for delay.
Ckielstra, Thanks for the response. I happen to have an mbed LPC1768 dev board at home that I had bough ... |
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| Topic: HW SPI clocking 12 bits between SS... Can it be done? |
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| Andrei S Replies: 14 Views: 24358 |
Forum: General CCS C Discussion Posted: Fri Aug 08, 2014 9:38 am Subject: HW SPI clocking 12 bits between SS... Can it be done? |
| Thanks for details. The PIC has no time critical duties in my application and the SPI data will be fetched at only 5hz to update a UI. The FPGA itself is doing all the work. Perhaps I will use the ... | |
| Topic: HW SPI clocking 12 bits between SS... Can it be done? |
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| Andrei S Replies: 14 Views: 24358 |
Forum: General CCS C Discussion Posted: Fri Aug 08, 2014 8:58 am Subject: HW SPI clocking 12 bits between SS... Can it be done? |
| I have a 20Mhz ext osc running the PIC. Perhaps a newbie assumption that a bit-banging software spi using GPIO wouldn't keep up with the 1.25Mhz FPGA clock? | |
| Topic: HW SPI clocking 12 bits between SS... Can it be done? |
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| Andrei S Replies: 14 Views: 24358 |
Forum: General CCS C Discussion Posted: Fri Aug 08, 2014 8:24 am Subject: HW SPI clocking 12 bits between SS... Can it be done? |
| Hi, I'm new to PIC's and the forum so please go easy...
I'm trying to interface with an existing FPGA design (meaning I can't change it) using a 18F4550 as a SPI slave. On a scope I can clearly ... |
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