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  Topic: LoRaWAN stack
Donatello

Replies: 15
Views: 44230

PostForum: General CCS C Discussion   Posted: Wed Jun 10, 2020 4:32 am   Subject: LoRaWAN stack
Thank you Ttelmah,
I have to transmit a simple data from multiple weather stations to a gateway. In this application LoRa is very convenient.
Without a LoRaWAN, my doubt are:
1) collisions when mul ...
  Topic: LoRaWAN stack
Donatello

Replies: 15
Views: 44230

PostForum: General CCS C Discussion   Posted: Wed Jun 10, 2020 2:29 am   Subject: LoRaWAN stack
Dear All,
I would like to make a LoRaWAN (868MHz) network with EByte LoRa modules. But I need a LoRaWAN stack. I read that Microchip has a plug-in but I was unable to download it. Anyone know a libra ...
  Topic: SPI: data received with 1 bit shift to the right [Solved]
Donatello

Replies: 12
Views: 26362

PostForum: General CCS C Discussion   Posted: Wed Mar 18, 2020 3:21 pm   Subject: SPI: data received with 1 bit shift to the right [Solved]
Dear Ttelmah, thank you very much!
This is the right work around for the dsPIC33EPXXGS50X family. I just added the output_high on the clock pin.

I report your code here with this setting, maybe i ...
  Topic: SPI: data received with 1 bit shift to the right [Solved]
Donatello

Replies: 12
Views: 26362

PostForum: General CCS C Discussion   Posted: Wed Mar 18, 2020 11:22 am   Subject: SPI: data received with 1 bit shift to the right [Solved]
OK, I don't use that PIC but 3 things I can think of...

1) check the listing to confirm the hardware SPI peripheral is being used....

2) check the compiler version for 'bugs'

3) check the PI ...
  Topic: SPI: data received with 1 bit shift to the right [Solved]
Donatello

Replies: 12
Views: 26362

PostForum: General CCS C Discussion   Posted: Wed Mar 18, 2020 10:14 am   Subject: SPI: data received with 1 bit shift to the right [Solved]
The datasheet says that the clock should idle high (CPOL=1), and the data
should be read on the rising edge of the clock (CPHA=1). This is SPI
mode 3. However there is also t1, which says you must ...
  Topic: SPI: data received with 1 bit shift to the right [Solved]
Donatello

Replies: 12
Views: 26362

PostForum: General CCS C Discussion   Posted: Wed Mar 18, 2020 6:41 am   Subject: SPI: data received with 1 bit shift to the right [Solved]
I downloaded the datasheet, max speed seems to be 4.8KHz, so I'd really slow down the SPI speed !
maybe try at 5,000 ??

I couldn't easily see the SPI mode in the datasheet...

The AD7190 is a 24 ...
  Topic: SPI: data received with 1 bit shift to the right [Solved]
Donatello

Replies: 12
Views: 26362

PostForum: General CCS C Discussion   Posted: Wed Mar 18, 2020 6:14 am   Subject: SPI: data received with 1 bit shift to the right [Solved]
SPI has 4 modes.... since mode 0 doesn't work, try mode 1 !!
Someone will probably post the 'code cheat' that lists the 4 modes as defines....I can't member stuff like that anymore,sigh.

Thanks t ...
  Topic: SPI: data received with 1 bit shift to the right [Solved]
Donatello

Replies: 12
Views: 26362

PostForum: General CCS C Discussion   Posted: Wed Mar 18, 2020 5:57 am   Subject: SPI: data received with 1 bit shift to the right [Solved]
Dear All,
I use DSPIC33EP16GS502 and AD7190 with a SPI communication.
In the AD7190 the SPI MODE is 3 because:
--> idle state for SPI clock is high (SPI clock polarity 1)
--> data is latched ...
  Topic: High speed PWM with incorrect frequency and jitter
Donatello

Replies: 10
Views: 22830

PostForum: General CCS C Discussion   Posted: Wed Mar 07, 2018 11:42 am   Subject: High speed PWM with incorrect frequency and jitter
It's behaving as if Aux is running off Frc/2 without the Aux PLL.

In my dspic the auxiliary clock ACLK is the clock for ADC and PWM modules.

If I use:
#use delay(CLOCK=140MHz, CRYSTAL=8MHz)
T ...
  Topic: High speed PWM with incorrect frequency and jitter
Donatello

Replies: 10
Views: 22830

PostForum: General CCS C Discussion   Posted: Wed Mar 07, 2018 6:12 am   Subject: High speed PWM with incorrect frequency and jitter


I use this code, but the PWM is unstable.

include <33EP64GS504.h>

#fuses ICSP1
#fuses NOJTAG
#fuses NOALTI2C1
#fuses NOALTI2C2
#fuses NOIOL1WAY

#fuses OSCIO ...
  Topic: High speed PWM with incorrect frequency and jitter
Donatello

Replies: 10
Views: 22830

PostForum: General CCS C Discussion   Posted: Tue Mar 06, 2018 3:05 pm   Subject: High speed PWM with incorrect frequency and jitter

How is a period of 0xFFFF going to give 460kHz?. This is out of spec for the chip 0x10 to 0xFFF8.

I used HSPWM_TIME_BASE_FROM_PHASE_REGS and set_hspwm_phase, then I did not take the value into Pe ...
  Topic: High speed PWM with incorrect frequency and jitter
Donatello

Replies: 10
Views: 22830

PostForum: General CCS C Discussion   Posted: Tue Mar 06, 2018 2:45 pm   Subject: High speed PWM with incorrect frequency and jitter
OK, I don't use 33 series PICs but..
shouldn't you have a 'clock= desired speed' line of code ??
You're right, in the "copy and paste" I missed delay instruction. Now, I edited my post. So ...
  Topic: High speed PWM with incorrect frequency and jitter
Donatello

Replies: 10
Views: 22830

PostForum: General CCS C Discussion   Posted: Tue Mar 06, 2018 12:16 pm   Subject: High speed PWM with incorrect frequency and jitter
Hello programmers,
these days I'm using the dspic33EP64GS504 (CCS 5.076 and MPLAB 4.05), I want to generate a frequency of 500kHz but without success.
I have no problem for frequencies lower than 46 ...
  Topic: Selected part does not have ICD debug capability
Donatello

Replies: 13
Views: 30039

PostForum: General CCS C Discussion   Posted: Tue Feb 20, 2018 12:16 pm   Subject: Selected part does not have ICD debug capability
Yes, I will contact CCS for debugging.
  Topic: Selected part does not have ICD debug capability
Donatello

Replies: 13
Views: 30039

PostForum: General CCS C Discussion   Posted: Fri Feb 16, 2018 11:39 am   Subject: Selected part does not have ICD debug capability
If I use
set_timer1(get_timer1()+X);
where X is any 16 bit number, Timer1 interrupt always works at 4ms. Shocked

I use in interrupt routine:
set_timer1(49536);
And in m ...
 
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