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Hi Ttelmah,
Yes, maybe I am using the function in an unexpected way.
Though, from searching the net to try and find the problem, it doesn't seem uncommon to use the compare function in this way to g ...

Hi All,
After working out what the CCS code for the Setup_ccp2 function was doing the problem becomes apparent, it is as Ttelmah suggested, the source for CCP2 is momentarily set to Timer1 before it ...

Hi Ttelmah,
Thank you very much for doing that, after your previous message I was going to go through it when I got into work this morning, but you've beaten me to it.

The great news is that this ...

Hi PCM programmer,
Thank you for your suggestion.
I have tried setting both timer1 only to 1:1 and all 3 timers to 1:1
Unfortunately it has no effect on the problem.
Interestingly slowing timer1 d ...

Hi, thank you for your reply.

does this happen if you leave timer1 enabled and shut off the
watchdog code?

Still the same problem.

this does not compile as is
SO where do you define CC ...

Does the chip's errata say anything about PWM at all? You might have discovered a chip (silicon) problem. Might be best to open a support ticket with Microchip.

Quite some time ago I found that a ...

Hi all,
Does anybody have any thoughts on this problem.

We have a product that uses the 18f24K22 PIC.
We have 2 pwm outputs generated by using the CCP2 and CCP3 modules in compare mode.
We noti ...

It's actually exactly the same problem as i had when i was trying to use the hardward I2C.
I put that down to that fact that the minimum I2C clock i could get with the hardward I2C is about 122khz.
...

Does it do this with a different I2C slave device?.

Key thing is that the slave device, can also hold the line low. This is 'clock stretching', and the master is then meant to stop till the line is ...

The 64MHz picture shows illegal start/stop conditions.

I2C should always start and end with SCL and SDA high.

I'd have to go look at the I2C spec again to be sure.. but I also provided a link i ...

As i mentioned above, i've found that at 64mhz PIC clock the I2C data output is idleling low.

I thought some pictures of this might be of interest.
No changes at all to the code between the 2 cloc ...

Thanks Ben, i was actually looking for a more up to data version of the SAA1064T data sheet.

Jim

What have you got as Cext?.
If you are running multiplexed, this determines all the update timings on the chip. There is a (hidden) minimum time between being able to do things, based upon this.

...

In your

#use i2c(master, sda=pin_c4, scl=pin_c3,SLOW=70000,FORCE_SW)

According to the manual, FAST=70000 would set the speed.

According to what i read FAST=70000 is identical to SLOW=70000, ...

It looks to me that he is writing to the display every 100+ms or so which is
really too fast. I would change the delay to 500ms at least.

I changed it to 1000ms , i just get 1 second updates of ...