CCS C Software and Maintenance Offers
FAQFAQ   FAQForum Help   FAQOfficial CCS Support   SearchSearch  RegisterRegister 

ProfileProfile   Log in to check your private messagesLog in to check your private messages   Log inLog in 

CCS does not monitor this forum on a regular basis.

Please do not post bug reports on this forum. Send them to CCS Technical Support
Confirmation please - compiler bug

 
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion
View previous topic :: View next topic  
Author Message
newguy



Joined: 24 Jun 2004
Posts: 1909

View user's profile Send private message

Confirmation please - compiler bug
PostPosted: Tue Oct 26, 2004 9:30 am     Reply with quote
Hi all,

I have ver 3.178 of the compiler (pcb, pcm & pch). I ran into a problem about a week ago and last night I finally nailed it.

I have a 18F452 with a 20 MHz crystal - HS mode. I measured the frequency on the pic's osc pins and it is indeed a stable 20 MHz. Anyway, here's the problem:

I used the compiler's setup wizard to create the project, and I wanted only one interrupt: timer0. I wanted it to be driven from the internal clock source, with no division, and 8 bits. The wizard correctly states that the overflow will be 51.2 us. (200 ns internal clock * 256 = 51.2 us)

The relevant code generated by the CCS wizard is:
Code:
setup_timer_0(RTCC_INTERNAL|RTCC_8_BIT);


So I stupidly thought that it was indeed generating an interrupt every 51.2 us (I don't load timer0 with any value at all - I just let it run). Turns out my project behaved strangely, and it seemed to be a timing problem. Well the interrupt was occurring every 104 us, as measured by a scope. The ISR itself only takes a few cycles to run - basically just toggle a couple of lines, and that's it - therefore it's not a case of the ISR taking more than 51.2 us to execute and missing every odd timer0 overflow.

The .lst file had the answer: the code above loads the T0CON register with 0xC0 - which sets up timer0 with internal clock, but divided by 2!!!! The proper value should be 0xC8. If I manually set T0CON to 0xC8, the interrupt occurs every 51.2 us, just as it should.

Just wondering if CCS has fixed this in newer releases of the compiler? I checked the revision history, and I can't find any mention of timer0 since 3.178. Can anyone confirm this bug in the newest version of the compiler? If so, I'll report it to CCS.
Guest
PostPosted: Tue Oct 26, 2004 10:08 am     Reply with quote
confirmed with 3.212, but not tested with my proto-board

.................... setup_timer_0 ( RTCC_INTERNAL | RTCC_8_BIT );
0018: MOVLW C0
001A: MOVWF T0CON

workaround: try using RTCC_DIV_256 instead of RTCC_8_BIT

.................... setup_timer_0 ( RTCC_INTERNAL | RTCC_DIV_256 );
001C: MOVLW 87
001E: MOVWF T0CON

or, go edit the header file ... 18F452.H ... over here

#define RTCC_8_BIT 0x40 // modify to 0x48

and ... 18F458.H ... and ... all the 18Fxxx.H Shocked Exclamation

you should file a bug report.

Thanks a lot and best wishes
Guest
PostPosted: Tue Oct 26, 2004 10:27 am     Reply with quote
sorry, RTCC_DIV_256 won't work, my mistake.

time to sleep ... bye.
Guest
Not a bug
PostPosted: Tue Oct 26, 2004 10:33 am     Reply with quote
18F452.H
Code:
#define RTCC_DIV_1      8
#define RTCC_DIV_2      0
#define RTCC_DIV_4      1
#define RTCC_8_BIT      0x40


so, the right way to set it up is ...

Code:

setup_timer_0 ( RTCC_INTERNAL | RTCC_8_BIT | RTCC_DIV_1 );


Cheers Very Happy
newguy



Joined: 24 Jun 2004
Posts: 1909

View user's profile Send private message

PostPosted: Tue Oct 26, 2004 11:32 am     Reply with quote
Quote:
18F452.H
Code:
#define RTCC_DIV_1 8
#define RTCC_DIV_2 0
#define RTCC_DIV_4 1
#define RTCC_8_BIT 0x40


so, the right way to set it up is ...

Code:

setup_timer_0 ( RTCC_INTERNAL | RTCC_8_BIT | RTCC_DIV_1 );


Actually, I tried that. I don't know what happened, but I can tell you that my application stopped running completely. As soon as I set the T0CON register manually to the correct value, then it worked.

My point is that the *wizard* told me that the timer0 overflow will be 51.2 us, when it is in fact 104 us. Either way, it's still a bug.
Guest
PostPosted: Tue Oct 26, 2004 11:38 pm     Reply with quote
Yes, there is a bug, somewhere. I suggest to call it a "Wizard bug", or, "IDE bug", instead of compiler bug. The buggy one is pcw.exe, the IDE.

I am happy with the following code telling me that ccsc.exe and pch.dll, the compiler, is ok.

Code:

....................    setup_timer_0 ( RTCC_INTERNAL | RTCC_8_BIT | RTCC_DIV_1 );
0014:  MOVLW  C8
0016:  MOVWF  T0CON
....................
....................    setup_timer_0 ( RTCC_INTERNAL | RTCC_8_BIT              );
0018:  MOVLW  C0
001A:  MOVWF  T0CON
....................
....................    *(int8 *)0xFD5 = 0xC8;
001C:  MOVLW  C8
001E:  MOVWF  T0CON


Best wishes Very Happy
Display posts from previous:   
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion All times are GMT - 6 Hours
Page 1 of 1

 
Jump to:  
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum


Powered by phpBB © 2001, 2005 phpBB Group