We are using 18F4525 and PCH Compiler.
I got all ready three interrupt and will be more two interrupts.
What happen if ISR of one interrupt is serving and at the same time
Timer0 overflows means RTCC interrupt generates?
Will RTCC interrupt will be served after servising the current interrupt?
I really got problem in generating the output frequency.
Can anybody give idea, How can I handle of the interrupt properly
without missing any of them?
If you can give example of any two interrupt then will be helpful to
write for all other interrupts.
Thank u....
asmallri
Joined: 12 Aug 2004 Posts: 1635 Location: Perth, Australia
Posted: Wed Dec 22, 2004 9:22 pm
The PIC18F family supports normal and high priority interrupts. A high priority interrupt can interrupt a normal priority interrupt. The CCS compiler supports a single high priority interrupt (using the FAST directive). If you need more than one high prioirty interrupt then you need to code your own interrupt handler.
The CCS compiler supports the ability to "prioritize" normal interrupts. This means this is you have say 4 normal priority interrupt handlers this determines which handler gets first chance to process the interrupt. A normal priority interrupt cannot interrupt an existing normal priority interrupt handler unless you specifically reenable interrupts (bad idea).
When multiple interrupts of ther same priority occur they are not lost unless multiple interrupts of the same type occur before the handler is given control. This is why it is a bad idea to use delay functions in an interrupt handler and why interrupt handlers are keep very short. _________________ Regards, Andrew
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