18F47J13 clock configuration

[peterpanic]

The 47J13 has a very competent (i.e. complex) clock configuration, and I want to use the internal oscillator at 8MHz to drive the 96MHz PLL. It is far from clear what the "magic spells" are.

I currently have (set by the project wizard)

[PCM programmer]

I don't have this PIC to test, but try this LED blinking program and
see if it works:

[peterpanic]

> try this LED blinking program and see if it works:

works fine, except the actual delay period measures 1500ms, not 500. But at least the compiler doesn't barf. Working on it, and will report...
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- peter -

[peterpanic]

Looks to me like two compiler bugs; the first is that the compiler doesn't "understand" the 96MHz PLL, and the second is that when using the ICD U-64, the config words get mangled - as well as changing the DEBUG and STVREN bits it also changes PLLSEL and WTDPS1 bits. Reported (not via the IDE reporting system which seems to be broken for me).
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- peter -

[dyeatman]

Where did you get the info that the PLL went to 96MHZ? From page
11 of the data sheet:

[peterpanic]

PLL runs at 96MHz, its output is divided by two to provide the 48MHz (max) processor clock.

p35 of data sheet: "The PIC18F47J13 provides two PLL circuits: a 4x multiplier PLL and a 96 MHz PLL enabling 48 MHz operation from the 8 MHz
internal oscillator."
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- peter -

[Ttelmah]

I always start by working out what bits have to be set where to do what I want.

So, working through the clock diagram from fig 3-1, we need FOSC:2=0 to say feed the internal oscillator to the PLL. Then PLLSEL set to 0. Then PLLDIV set to 110, and either PLLEN, or CFGPLLEN set to 1. FOSC 2:0 = something other than 00. OSCCON 1:0 = 00.

So then look where these come from. CFGPLLEN, PLLDIV, PLLSEL, & FOSC, are all in the fuses, while OSCCON is a user setting.

Then step into the device editor, and look at what CCS setting sets these bits. This is the little window in the top right of device editor, which shows CCS fuse 'names', and what registers/bits are masked and set for each of these. So, need to get : xxx1110x in the first register and xxxxx01x in the second. PLL2, correctly gives the low nibble for the first, and PLLEN, the high nibble. Then INTRC_PLL, or INT_RC_PLL_IO look to give the required bits in the second byte. PLLSEL requires bit 2 of byte 5, and this is set by the PLL fuse.
So we should need:

PLL, INTRC_PLL_IO, PLL2

Then 'be careful' CCS has become increasingly complex regarding the 'clock' setting. If you say 'crystal', 'internal', or other similar keywords, it overrides individual fuses to setup what it 'thinks' is right. Safer, to just use the 'clock' keyword, which appears to always leave your fuses as they are. This may be the 'core' problem.

So, now all that is needed is the OSCCON bits. Two choices 'setup_oscillator', or go 'DIY'. Looking at the setup_oscillator settings, 'OSC_NORMAL' is '00' for the required bits. This should be the 'default', but select it anyway.

So then trying:

[peterpanic]

[Ttelmah]

OK.
The accuracy of this, suggests it is from the 8MHz source divided down, rather than from the separate INTRC source.
So only routes are:

OSCTUNE 7 = 1 (fair enough we are not changing this, might well be 1).
OSCCON 6:4 = 000 (OK, we set this whole register to 0).

Then _either_ OSCCON 1:0 = 11, or FOSC 2:1 = 00, to give 31KHz out.

Now, for me, OSCCON 1:0, is set to 00, and the fuses have FOSC 2:1 set to 10

What do these show for your, if you load the code into a simulator like MPLAB?.

What compiler version are you using?.

Best Wishes

[peterpanic]

[peterpanic]

I also see there is a Mchip silicon errata item which explains that, even though it's not used, you have to set the INTOSC prescaler selector to 4MHz or 8MHz.
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- peter -