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nathani
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| RCON WatchDog on 18F6680 |
 Posted: Tue Mar 13, 2007 2:34 pm |
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I am using compiler version 3.184.
I have designed some code to detect the last reset condition. I set all the RCON bits to 1 and set STKFUL and STKUNF to 0. Then by reading the RCON and the two stack bits on power up, I can determine the last reset condition. For the most part this works great. However whenever I get a watchdog reset it has the same value as "MCLR reset during normal operation." I've manually checked the value using our CAN network. Is this possibly a problem with this particular PIC?
Below is the code I've written
| Code: |
/**************************************************************************/
/* Detemines the last reset cause and increments appropriate counter */
void determine_reset_cause(void)
{
resetCause = RCON;
resetCause <<= 3; //Shif out unwanted values and make room for stack flags (below)
if(bit_test(STKPTR,6)) bit_set(resetCause,0);
if(bit_test(STKPTR,7)) bit_set(resetCause,1);
bit_clear(STKPTR,6); //Set Registers to Know Sate
bit_clear(STKPTR,7);
bit_set(RCON,0);
bit_set(RCON,1);
bit_set(RCON,2);
bit_set(RCON,3);
bit_set(RCON,4);
} |
According to this I should see a 0xF8 upon MCLR. That checks out, but I also see a 0xF8 after a WatchDog Reset. |
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Ttelmah
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| Posted: Tue Mar 13, 2007 3:48 pm |
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Look at the defintions. Note that the bits concerned, are left _unchanged_ by a watchdog reset, and _set_ by a MCLR reset. You must therefore _clear_ at least one of these, to detect the difference between these two reset types. Normally PD, is cleared, since this then allows the other bits to be used to detect the other types of reset.
Best Wishes |
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nathani
Guest
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| Posted: Tue Mar 13, 2007 3:53 pm |
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| Hmmm, I've programmed another 18F6680 on a completely different type of board and the watchdog seems to detect properly on this board, I'm going to investigate hardware issues. |
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nathani
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| Posted: Tue Mar 13, 2007 3:58 pm |
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Ttelmah, thanks for the response.
I have looked at the definitions. I don't know if you analyzed my code or not. Also the bits are left unchanged by a MCLR and set by the watchdog reset, according to the data sheet I am reading.
I read your previous post on this before designing this function, so thanks for that as well,
Nathan |
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nathani
Guest
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| Posted: Tue Mar 13, 2007 4:20 pm |
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| Hmmm, MCLR looks steady as a rock. I checked with an oscilliscope. |
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nathani
Guest
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| Posted: Tue Mar 13, 2007 4:28 pm |
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| Anyway, thanks for the help, suppose I'm on my own on this one, as it's most likely a hardware or code problem, from what I'm seeing. |
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nathani
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| Posted: Tue Mar 13, 2007 5:05 pm |
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Alright, last post, I swear.
Cause of the problem was that I had enabled and done a reset on the watchdog timer before I read RCON. I didn't see this little beauty till now. Anyway, I makes perfect sense, since in my scheme the only difference between MCLR and watchdog is TO. I had already checked this on the code that was working, so it... surprise... worked. Anyways, thanks again |
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Ttelmah
Guest
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| Posted: Wed Mar 14, 2007 3:52 am |
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Aargh. Typical.
I was going to say in my post, to be sure to check the bits _early_ in the code, but thought 'not worth it', and it was the answer!...
Best Wishes |
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