CCS C Software and Maintenance Offers
FAQFAQ   FAQForum Help   FAQOfficial CCS Support   SearchSearch  RegisterRegister 

ProfileProfile   Log in to check your private messagesLog in to check your private messages   Log inLog in 

CCS does not monitor this forum on a regular basis.

Please do not post bug reports on this forum. Send them to CCS Technical Support

Bootloader for the J series

 
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion
View previous topic :: View next topic  
Author Message
libor



Joined: 14 Dec 2004
Posts: 288
Location: Hungary

View user's profile Send private message

Bootloader for the J series
PostPosted: Sun Jul 15, 2007 1:38 pm     Reply with quote

I am looking for a serial bootloader to be used in a 18F25J10. The challenge is, these J series chips have a flash erase block size of 1024 bytes, and a write block size of 64 bytes, so the 'normal' bootloaders supposing equal size erase and write blocks do not work.
Before I begin to write my own (or modify an existing one) I decided to ask you, guys, if someone has experience with these chips in this regard.
asmallri



Joined: 12 Aug 2004
Posts: 1636
Location: Perth, Australia

View user's profile Send private message Send e-mail Visit poster's website

PostPosted: Sun Jul 15, 2007 2:23 pm     Reply with quote

The J series has lower flash program memory endurance. I implemented a number of techniques in my Ethernet bootloader for this family to minimize the number of writes by, reading the current page of program memory (in repronce to an Intel hex type 4 record) and caching the subsequent writes to the this target page in shadow ram until the bootloader was finished or attempted to cross the current 1K boundary at which point I then compare the target page contents with the contents of the shadow ram and only perform and erase - write sequence on the page if there is a difference between them.
_________________
Regards, Andrew

http://www.brushelectronics.com/software
Home of Ethernet, SD card and Encrypted Serial Bootloaders for PICs!!
libor



Joined: 14 Dec 2004
Posts: 288
Location: Hungary

View user's profile Send private message

PostPosted: Mon Jul 16, 2007 2:24 am     Reply with quote

Thank you for the clues. I was thinking in the same way.

But - raising the challenge - these chips have only 1024 bytes of RAM, so how can I assign a shadow ram using literally all bytes of ram, with not a single byte left for the working variables ? (fortunately I would need not that many variables, maybe just 2-3: can I save them in an unused system register, like the unused stack locations, or some FSRxx register ? What do you think about it ?

Or as an alternative: Can I always rely on the .hex file files data coming in sequence of increasing addresses ? I looked at a few, they were all filling the flash from the beginning to the end with no jumping about. (you would have troubles with the 1K shadow ram buffer anyway if the .hex file address would jump about and return a second time to the same 1K block only partially filling it at a time ?)

If the .hex file's addresses are always continuously increasing, I can simply erase the next 1024 bytes when the write block crosses a 1024 boundary. (this is exactly what the built-in write_program_memory() function does btw.)
Only some extra hassle is required with the reset vectors' block and the fuses' block (these chip write the fuses in the last 8 bytes of the flash)
asmallri



Joined: 12 Aug 2004
Posts: 1636
Location: Perth, Australia

View user's profile Send private message Send e-mail Visit poster's website

PostPosted: Mon Jul 16, 2007 8:47 am     Reply with quote

libor wrote:
Thank you for the clues. I was thinking in the same way.

But - raising the challenge - these chips have only 1024 bytes of RAM, so how can I assign a shadow ram using literally all bytes of ram, with not a single byte left for the working variables ?


My bootloader is an incremental bootloader - meaning you can change just a single byte at a time. This is what requires the shadow block approach. The advantage with this approach is that the program memory can also be used to simulate EEPROM by enabling the modification of bytes anywhere in the program memory. In the case of J series PICs with a 1024 erase page size and only 1K of RAM this model is not viable. With these PICs I think the solution is to perform an 1K page erase when a new type 4 record is processed. This assumes the hex file is structured in such a manner that all records with a 1K page are contained within the same type 4 record boundary. This would appear to be a reasonable assumption for the typical compiler output.

Quote:

(fortunately I would need not that many variables, maybe just 2-3: can I save them in an unused system register, like the unused stack locations, or some FSRxx register ? What do you think about it ?


You need to get the data into the PIC somehow. This typically requires buffering which will be challenging to implement without RAM.
_________________
Regards, Andrew

http://www.brushelectronics.com/software
Home of Ethernet, SD card and Encrypted Serial Bootloaders for PICs!!
Display posts from previous:   
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion All times are GMT - 6 Hours
Page 1 of 1

 
Jump to:  
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum


Powered by phpBB © 2001, 2005 phpBB Group