Joined: 20 Nov 2007 Posts: 2128 Location: albany ny
high baud warnings on many 16C products
Posted: Sat Jun 06, 2009 4:41 pm
Have been looking at a legacy item - product with serial RS232 on 16c74a
that is getting some changes ( client has in the thousands of un programmed PICS they expect to continue to use).
Anyway-
I want to increase the baud rate to match some other equipment - now 9600 - going up to 38400 - 8-1-N AND using an optimal oscillator for the PIC.
XTAL= 4.9152Mhz BRG=1 SPBRG=7 err = 0%
BUT see this warning in the data sheet :
----------------
Note: For the PIC16C73/73A/74/74A, the asynchronous high speed mode (BRGH = 1) may experience a high
rate of receive errors. It is recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0
can support, refer to the device errata for additional information, or use the PIC16C76/77.
THE SAME kind of language is printed for the 16C6X and other families
ALSO steering the user towards the two 'top' models in each family as a way to avoid this risk.
The Microchip web site added NOTHING - in fact the official silicon errata sheet merely quotes the language above with no explanation.
And offers NO extra information at all.
WHAT ON EARTH IS THE REASON FOR THE WARNING ?
and why do BOTH of the 'C families share this "risk" ONLY on the smaller memory versions of the parts ?
(especially since I will be using the proven serial ISR receive buffer).
This is weirdly puzzling and PATHETIC - in that there is NO safe max baud stated in the warning either.
Is this a deep silicon problem that they are not being forthcoming about ?
Any insights?
dyeatman
Joined: 06 Sep 2003 Posts: 1934 Location: Norman, OK
Posted: Sat Jun 06, 2009 5:01 pm
From a quick calculation it appears you would be fine with BRGH=0 and SPBRG=1. That should yield 0% error at 38,400.
Table 12-4 shows BRGH=0 being able to make 76.8K at your clock frequency. At the bottom of the cell in the table for 5.0688MHZ clock it shows the MAX (HIGH 79.2KB) and MIN (LOW 0.3094KB) baud rates supported at that frequency. _________________ Google and Forum Search are some of your best tools!!!!
Joined: 20 Nov 2007 Posts: 2128 Location: albany ny
angst not my problem
Posted: Sat Jun 06, 2009 10:03 pm
i already know what works and doesn't for bauds
that was NOT what is on my mind
the heart of the matter was:
---------------
Quote:
per the data sheet warning about BRG=0
why do BOTH of the 'C families share this "risk of errors" BUT ONLY on the smaller memory versions of the parts ?
these have HARDWARE uarts YET they say C74a "risky"
but C77 - no problem
ditto the c64 vs c67
THATS what i'm trying to get info on
PCM programmer
Joined: 06 Sep 2003 Posts: 21708
Posted: Sat Jun 06, 2009 11:18 pm
The answers are more likely be on the Microchip website, not here.
According to the USART reference manual, those PICs use a different
sampling scheme than all other PICs, when BRGH = 1 (see page 13):
http://ww1.microchip.com/downloads/en/DeviceDoc/31018a.pdf
Apparently that method wasn't reliable.
Joined: 20 Nov 2007 Posts: 2128 Location: albany ny
very interesting
Posted: Sun Jun 07, 2009 7:39 am
so it comes down to an early(ier) sampling method than is used on later parts.
Thanks PCM - SO now i'm going to have to try loop back experiments to see -whazzup
early sampling - or not - i HAVE to find out if the ISR capture method fails on these parts - with an extended "marching" bit test connected to a PC
( with a 6" cable and an edgeport actually )
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