Understanding interrupt handler on PIC18

[Mortenc]

Hello super forum,

I want to use both high and low priority interrupts.
My question is: What happen to my low priority interrupt when the high priority interrupt comes and the low priority interrupt is running?

Does the return from high priority interrupt then return to the low priority interrupt?

[Ttelmah]

First thing, you have to distinguish two different 'types' of priority.

Historically, CCS, has a 'priority' instruction. This affects _only_ the order in which interrupts are checked within the interrupt handler. If not present, this is instead set by the order the interrupts are defined in the code. This 'priority', has no ability for one interrupt to be called inside another. This is available for all chips with interrupts.

Then you have the 'hardware priority'. This is not available on the PIC12/PIC16 chips. It allows two separate interrupt handlers to be used. This is enabled, by selecting 'HIGH_INTS=TRUE' in the device configuration, and then flagging the individual interrupt handler as 'HIGH', or 'FAST' (use the first, unless you very specifically need the second - the second does effectively the same job as #int_default for the low priority interrupts, adding no code to save registers etc., to the handler...). With this done, you then have two complete global interrupt handlers. The first 'low priority' one, handles all the interrupts not flagged as 'HIGH', and the second, the hardware 'high priority' interrupts. These interrupts can then interrupt the low priority interrupts, or the normal code, and since the handlers are separate, there is no 're-entrancy' problem, but not each other.
Big 'caveat' here. If you declare any interrupt handler as 'HIGH', and you also have INT0 (INT_EXT) in use, this interrupt will also be set as 'HIGH'. This is a hardware limitation of the PIC, (not CCS's fault!...), but it does mean that it is worth avoiding INT_EXT, unless you _want_ it to he high priority.....

Having high priority hardware interrupts enabled, will make the interrupt latency to the normal interrupts, slightly worse (the 'RETFIE 1' instruction, which saves the need to save a couple of the registers on entry to the interrupt handler, is used by the high priority handler).

Best Wishes

[Mortenc]

Thanks for respond,

To be sure I understand this correct.

I use PIC18 family. (I known that PIC12 and PIC16 can't do this).

I want to use:

#INT_CCP1 HIGH
#INT_RDA
#INT_TBE
#INT_RDA
#INT_TIMER1

I you can see one with high priority and 4 with low priority.
The setup for the CCP1 shall be with timer3.

After CCP1 interrupt has taken place the program will return to the other interrupt if they where active when CCP1 was comming. Right?

[Ttelmah]

Yes.
I see you are not using INT_EXT, so that caveat vanishes. :-)
You are listing INT_RDA twice. Presmably (hopefully) the second is INT_RDA2?.

Best Wishes

[Mortenc]

Sorry the failure in listing,

I'm only want to using INT_RDA one time.

1000 thanks for your help.

[neverlog]

[Ttelmah]

No.
Look at the data sheet..
The 'point' about 'INT0', is it doesn't have a programmable bit specifying whether it is to be high priority or not.
If (for example), you go to the data sheet for the 18F4550, then select the 'interrupts' section, and look at the diagram for 'interrupt logic', you will find that all the interrupts except this one, are present on both the 'high', and 'low' branches of the interrupt hardware wiring, with three inputs to each gate selecting them, one from each of the enable, flag, and priority bits (and inverted from the priority bit, on the 'low' branch). INT0, alone, does not have any connections at all to the low priority branch.

Best Wishes

[neverlog]

Thank you, Ttelmah.