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jocaropi
Joined: 25 Jun 2014
Posts: 18
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| DSPIC33EP512GP502 not working properly. |
 Posted: Fri Jul 18, 2014 3:25 am |
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Hello, I'm programing a DSPIC33EP512GP502 with a pickit3.
I'm using the .h file of the DSPIC33EP256GP502 because my ccs version doesn't have the 512 model, but in theory the chips are identical.
My problems are that I can't configure the clock speed neither the spi communication properly.
I'm trying to blink a LED but it blinks 18 times slower than expected.
Also I'm trying to drive a lcd display with a code that worked fine with a 8bit pic a little slower than the one I'm using right now, but It doesn't work, could anyone help me, please? here it is the code:
| Code: |
#include <33EP256GP502.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#FUSES NOWDT //No Watch Dog Timer
#FUSES NOJTAG //JTAG disabled
#FUSES ALTI2C2 //I2C2 mapped to ASDA2/ASCL2 pins
#FUSES NOWINDIS //Watch Dog Timer in Window mode
#FUSES ICSP3
#FUSES HS
#FUSES PR_PLL
#use delay(clock=140000000)
#use spi(MASTER, SPI1, MODE=0, BITS=8, stream=FAST)
void main(){
output_high(PIN_A4);
while(TRUE){
delay_ms(500);
output_toggle(PIN_A4);
}
} |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19552
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| Posted: Fri Jul 18, 2014 3:46 am |
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What compiler version?.
However key thing missing, is you are not giving the compiler any chance!.....
To calculate the divisors and multipliers for the PLL, the compiler needs to know both the target frequency, and the crystal frequency. Without this, it can't calculate these.
#use delay(clock=140MHz, crystal=xxxMHz) |
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jocaropi
Joined: 25 Jun 2014
Posts: 18
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| Posted: Fri Jul 18, 2014 3:48 am |
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Hi, I'm not using any crystal.
The pic is capable of achieving the 140MHz with the internal oscillator. |
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jocaropi
Joined: 25 Jun 2014
Posts: 18
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| Posted: Fri Jul 18, 2014 3:57 am |
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I have tried
#use delay(clock=140MHz, internal=8MHz)
even
#use delay(clock=8000000)
but the LED still blinks every 9 seconds. |
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joergn
Joined: 15 Jul 2010
Posts: 15
Location: Hamburg Germany
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| Posted: Fri Jul 18, 2014 6:01 am |
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Hi, try
#use delay(internal=140000000) |
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jocaropi
Joined: 25 Jun 2014
Posts: 18
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| Posted: Fri Jul 18, 2014 6:15 am |
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| Already did, nothing. |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19552
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| Posted: Fri Jul 18, 2014 6:53 am |
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| jocaropi wrote: | Hi, I'm not using any crystal.
The pic is capable of achieving the 140MHz with the internal oscillator. |
You are selecting the crystal oscillator. This is what 'HS' implies. You need to select FRC_PLL.
Also though, you have not answered the question about compiler version?. This matters. On some older compilers the automatic selection didn't work, and you had to manually use setup_oscillator in the code:
setup_oscillator(OSC_INTERNAL, 140000000);
On modern compilers,
#use delay(internal=140000000)
Should work provided you get rid of the oscillator selection in the fuses. |
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jocaropi
Joined: 25 Jun 2014
Posts: 18
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| Posted: Fri Jul 18, 2014 7:04 am |
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Hello again,
I already changed the fuse to FRC_PLL some time ago.
I have tried the setup_oscillator thing but nothing works, it's very strange.
I'm using the v5.008 |
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joergn
Joined: 15 Jul 2010
Posts: 15
Location: Hamburg Germany
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| Posted: Fri Jul 18, 2014 8:14 am |
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You have to verify out of the SFR registers if the clock settings are set correctly, because you mentioned that those chips should be identical, but may be not ??
If in case the behaviour is caused by an error of the compiler or a wrong selected header file, this is the way to check it.
The register adresses etc. and the correct settings tells you the data sheet
and the errata ;-)
Or you update your compiler, if you don't want to do it manualy. |
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jocaropi
Joined: 25 Jun 2014
Posts: 18
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| Posted: Fri Jul 18, 2014 8:22 am |
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I've been investigating and it seems to be that the new chips have a special way of configuring the PLL. I've configured it right with the xc16 compiler and works ok, but it's a difficult compiler, and I don't know how to translate the rest of the program.
Also I don't know how to configure the bits needed in CCS.
On xc16 the configuration needed was:
| Code: |
CLKDIVbits.PLLPRE0 = 0;
CLKDIVbits.PLLPRE1 = 0;
CLKDIVbits.PLLPRE2 = 0;
CLKDIVbits.PLLPRE3 = 0;
CLKDIVbits.PLLPRE4 = 0;
PLLFBDbits.PLLDIV0 = 0;
PLLFBDbits.PLLDIV1 = 1;
PLLFBDbits.PLLDIV2 = 0;
PLLFBDbits.PLLDIV3 = 1;
PLLFBDbits.PLLDIV4 = 0;
PLLFBDbits.PLLDIV5 = 0;
PLLFBDbits.PLLDIV6 = 1;
PLLFBDbits.PLLDIV7 = 0;
PLLFBDbits.PLLDIV8 = 0;
CLKDIVbits.PLLPOST0 = 0;
CLKDIVbits.PLLPOST1 = 0;
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joergn
Joined: 15 Jul 2010
Posts: 15
Location: Hamburg Germany
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| Posted: Fri Jul 18, 2014 8:50 am |
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If you want to SFR registers you define them with #word:
#WORD CLKDIV = 0x0744 //this is the correct adr
#WORD PLLFBD = 0x0746 //this is the correct adr
now you can also define also the bits like:
#BIT CLKDIVb0 = CLKDIV.0
writing
CLKDIVb0=1;
or you write the full SFRreg by:
CLKDIV = 0b1010101010101010; |
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jocaropi
Joined: 25 Jun 2014
Posts: 18
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| Posted: Fri Jul 18, 2014 9:13 am |
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I've writen the following, but doesn't work:
| Code: |
#word CLKDIV = 0X0744 //CLOCK DIVISOR REGISTER
#word PLLFBD = 0X0746//PLL FEEDBACK DIVISOR REGISTER
#bit CLKDIVb0=CLKDIV.0//‘N1’, PLL prescaler ->N1=2
#bit CLKDIVb1=CLKDIV.1
#bit CLKDIVb2=CLKDIV.2
#bit CLKDIVb3=CLKDIV.3
#bit CLKDIVb4=CLKDIV.4
#bit CLKDIVb5=CLKDIV.5
#bit CLKDIVb6=CLKDIV.6//‘N2’, PLL prescaler ->N2=2
#bit CLKDIVb7=CLKDIV.7
#bit CLKDIVb8=CLKDIV.8
#bit CLKDIVb9=CLKDIV.9
#bit CLKDIVb10=CLKDIV.10
#bit CLKDIVb11=CLKDIV.11//DOZE Mode Enable bit
#bit CLKDIVb12=CLKDIV.12//Processor Clock Reduction Select bits->1:1
#bit CLKDIVb13=CLKDIV.13
#bit CLKDIVb14=CLKDIV.14
#bit CLKDIVb15=CLKDIV.15
(in main)
PLLFBD=0b001001010;
CLKDIV=0b0000000000000000;
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Ttelmah
Joined: 11 Mar 2010
Posts: 19552
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| Posted: Fri Jul 18, 2014 12:13 pm |
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OK. Possibly not surprised, as 5.008, was still when V5, was in it's 'infancy', but it was 98% working by then. Looks as if you may have found a place where it isn't...
You need to unlock the registers before you can write to them. Do a search here. Code to reconfigure the oscillator was published when these chips were new, and this was a common problem. |
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jocaropi
Joined: 25 Jun 2014
Posts: 18
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| Posted: Fri Jul 18, 2014 2:08 pm |
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I'm searching in the forum for long but I can't find anything :/
How can I unlock the registers? |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19552
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| Posted: Fri Jul 18, 2014 2:59 pm |
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I found six threads with this covered in a straight search on the site.
However these all use assembler, which is actually unnecessary.
So:
| Code: |
#word OSCCON=getenv("SFR:OSCON")
#byte OSCCONL=OSCCON
#byte OSCCONH=OSCCON+1
#bit OSWEN=OSCON.0
//Interrupts must be disabled
OSCCONH=0x78;
OSCCONH=0x9A; //These must execute one after the other
OSCCONH=newvalh; //New value for this register. Must write as a single
//byte immediately after the unlock
OSCCONL=0x46;
OSCCONL=0x57; //Unlock the low register
OSWEN=TRUE; //enable the write
//Now test if OSWEN==0. If it is the write succeeded.
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Now key is that you still cannot do certain direct changes. If (for instance) the chip is running Primary/PLL, then you have to switch to FRC (without PLL), and then to FRC/PLL.
Suggest you set the clock statement to CLOCK=140MHz, select the fuse FRC (without PLL), and then manually select FRC with PLL using the above sequence.
You don't write directlyy to the 'clock' bits in the top of OSCCONH. Instead you set the bits you 'want' in the 'NOSC' bits (10:8 in the OSCCON register), and when 'OSWEN' is triggered, the CPU switches to these.
It is in the 'oscillator' section of the full reference manual. |
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