CCS have a bug on interrupt handler?

[E_Blue]

PIC18F67J50
PLL_ON internal OSC

CCS V.5056

OSCTUNE=0x64
OSCCON=0x12

One level interrupts.(Legacy mode)

Time to time OSCTUNE change to 0x09, so PLL is off.

I put a breakpoint on memory change and stop at the input of interrupt handler routine; that is CCS code because I'm using CCS default interrupt handler.

Also PIE1 changes get TMR2IE and CCP1IE enabled and I specifically disable those interrupts at program start.

Any idea about how to solve this?
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Electric Blue

[Ttelmah]

I would suspect you have a hardware problem. You can get registers being corrupted, if you have inadequate smoothing on Vddcore. Look at the diagram for recommended connections. Are yours done like they suggest?.
Are you using the on-chip Vreg or an external supply?.
The ESR specification for this capacitor is vital to stability, as is how close it needs to be to the chip.

If you build the code with 'symbolic' mode selected, and look at the LST file, you can see that there is no instruction in the handler to touch the OSCCON register. The only time it touches this is a the very start to turn the PLL on at boot.
Similarly no hidden instructions accessing the interrupt enables.

Tested with your compiler version.

[E_Blue]

Thanks for your answer.
Can be a hardware problem but then Why the breakpoint always stops at the same instruction?

I have an LM2576 to get 4.3V, then an LDO to get 3.3V and then the internal LDO and every voltage with their own capacitors.
Also I put 100nF close to every VDD and AVDD and the PCB have four layers with GND mask.

I get before some troubles with BSR register being corrupted when I use two interrupt levels, that's why now I'm using only one.
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Electric Blue

[Ttelmah]

Generally hardware things like this will often just affect a few specific cells in memory.
My suspicion actually is that it is jumping or calling the interrupt handler, possibly with the wrong flags set.
Are you _sure_ about the ESR spec of the capacitor on Vddcore?. This one causes a lot of grief.
Can you step back to a really small test program, just setting up the interrupt, and the minimum hardware to see if the problem still appears.

[PCM programmer]

[Ttelmah]

Thanks PCM.

The reason I keep 'harping' back to this, is I wasted two days a little while ago. Was asked to come in and 'fix' a programming problem a company was having on a board based on the 87J50. Went in chased round the software, and after a few hours started throwing out code to try to track down what was wrong. Eventually found four bits in the Processor registers were changing without reason. Scratched my head, then started looking at the hardware. Board was one they had made 'in house', and looked fine, but eventually put a scope on the Vddcore line, and found it had a tiny oscillation at about 100MHz. Checked the cap spec and it looked OK (like the thread you point to), but had in my 'toolbox' some Murata ones the same size/value. Decided to substitute one of these, and as soon as I did, the board started behaving properly. There were only a couple of minor problems in the original code....

So I have seen a problem almost identical to the one being described here, caused by the wrong capacitor on Vddcore.

It needs to be 10uF, and needs a low ESR. I've seen 'conventional' electrolytic's be OK, if paralleled with a small ceramic, and also OSCON electrolytic ones be fine, or (honestly), use the ones that Microchip specify.