What is PLL?

[ressas]

What is PLL?

[Ttelmah]

Phase Locked Loop.

Standard way in electronics of generating a higher frequency from a source.
The 'classic' is a variable frequency RC oscillator, a divider and a phase
detector. Choose a particular division, and then compare the output signal
with the incoming source in the phase detector. If you are getting ahead
of the incoming signal you reduce the oscillator speed. If falling behind, you
increase the speed. So the oscillator then produces a signal that is the
'divider' times the incoming signal.
In the standard PIC version, it produces a signal 4* the source. Then in
the USB chips there is instead a version that produces 24 * the source. On
the DsPIC's and some of the later chips, you have the ability to specify the
division ratio, so the oscillator can produce a huge range of multiplication
factors.
It is also very commonly used in things like radios and phones, where in
many cases it is impossible to actually produce a crystal that runs at
the frequency you want, so instead you use a much easier to make
lower frequency, and a PLL to produce the required final frequency. This
is actually why it is being used in the PICs, since many now run well
above the maximum crystal frequencies available.

[ressas]

Thank you Ttelmah.
I would like to ask another question specific to 18f46k22.
On the first page of the datasheet, the expression "- 64 MHz performance
available using PLL – no external components required" appears.
When I say INTRC in fuses, I actually get 64 MHz from the OSC2 pin with
an oscilloscope. But because it is / 4 the pin works at 16MHZ right ?
So if I hadn't activated the PLL, how many MHz would I work ?

As the third:
Should I include the #fuse PLLEN statement in my code?
Or just:

[temtronic]

Quick answer.
16MHz....

Have a look at the datasheet, chapter2, figure 2-1, page 26 and follow the 'clock path'.

You'll see the various pathways you can get a 'clock' to the PIC. This PIC is easy to follow unlike the 4550 where there's a LOT of paths and combinations !!

Jay

[Ttelmah]

and OSC_64MHz, actually includes the PLL enable 'internally'. So you
automatically get the PLL when you use this and don't have to specify it.

[zeronix]

nice topic