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guy
Joined: 21 Oct 2005
Posts: 297
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| CLC for JK FLIPFLOP |
 Posted: Wed Aug 31, 2022 2:10 pm |
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(PIC16F18855)
Hi! I want to use the NCO with a clock half the speed of HFINTOSC. For this I want to use the CLC set up as a JK FLIPFLOP (freq. divider).
Configuring the CLC correctly seems impossible... 
If someone can post the setup code I would highly appreciate it.
Thanks!!! |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19559
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| Posted: Wed Aug 31, 2022 11:41 pm |
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This thread:
[url]
https://www.ccsinfo.com/forum/viewtopic.php?t=55128
[/url]
Has a CLC being setup as a flip flop.
Wrong clock source for you, but this is only the input selection.
Should give a good clue as to how to do this. |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19559
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| Posted: Thu Sep 01, 2022 1:30 am |
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Reading on, slightly puzzled. A divider would normally be done with a D
flip flop, not a JK flip flop.
You simply feed it's output inverted back to it's input and clock it from
your source clock. It's output then inverts every clock cycle. Result /2. |
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guy
Joined: 21 Oct 2005
Posts: 297
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| Posted: Thu Sep 01, 2022 1:04 pm |
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| Ttelmah wrote: | Reading on, slightly puzzled. A divider would normally be done with a D
flip flop, not a JK flip flop.
You simply feed it's output inverted back to it's input and clock it from
your source clock. It's output then inverts every clock cycle. Result /2. |
Thank you Ttelmah, it only goes to show I'm no expert... I wouldn't know how to configure it that way, I just want to move on with the project.
Any help would be appreciated. |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19559
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| Posted: Thu Sep 01, 2022 10:25 pm |
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No, actually this is historical.
In the first days of logic gates, JK flip flops were the first ones introduced.
They also involve one less gate than D flip flops. So the earliest books use
JK's for everything. However once D's became common, for dividers they
'took over'. For the CLC, either can be done, and there are less connections
to setup to use the D.  |
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