External ram CY62256LL-70PC read/write example

[vibrasys]

Hello there.
I tried to hook up a 62256 (CY62256LL-70PC),32kx8 ram chip through 2 latch chips,74hct373 on port D of a pic18F452 at 20mhz for addressing,port which is also shared for ram data i/o...seems i have a a bug in the code and can't figure it out.I get the same value when i read from both 0x105 and 0x106 address,and that is char 'A'.
Thank you in advance
here is the code

#include <18F452.h>
#device adc=8

#FUSES NOWDT //No Watch Dog Timer
#FUSES WDT128 //Watch Dog Timer uses 1:128 Postscale
#FUSES HS //High speed Osc (> 4mhz)
#FUSES NOPROTECT //Code not protected from reading
#FUSES NOOSCSEN //Oscillator switching is disabled, main oscillator is source
#FUSES BROWNOUT //Reset when brownout detected
#FUSES BORV20 //Brownout reset at 2.0V
#FUSES PUT //Power Up Timer
#FUSES STVREN //Stack full/underflow will cause reset
#FUSES NODEBUG //No Debug mode for ICD
#FUSES NOLVP //No low voltage prgming, B3(PIC16) or B5(PIC18) used for I/O
#FUSES NOWRT //Program memory not write protected
#FUSES NOWRTD //Data EEPROM not write protected
#FUSES NOWRTB //Boot block not write protected
#FUSES NOWRTC //configuration not registers write protected
#FUSES NOCPD //No EE protection
#FUSES NOCPB //No Boot Block code protection
#FUSES NOEBTR //Memory not protected from table reads
#FUSES NOEBTRB //Boot block not protected from table reads

#use delay(clock=20000000)
#use rs232(baud=115200,parity=N,xmit=PIN_C6,rcv=PIN_C7,bits=8,errors)

#define EnC_H PIN_B0 // Enable Control H address
#define EnC_L PIN_B1 // Enable Control L address
#define WE PIN_B4 // Write Enable
#define OE PIN_B3 // Output Enable
#define CS PIN_B2 // Chip select
#define Latch output_low
#define Release output_high

int16 init_address;
int8 adH, adL;
int8 data_inp, data_out=0;


void Write_61256(int16 address, int8 Data)
{
adH = make8(address,1);
adL = make8(address,0);


Latch(EnC_L);
output_d(adL);
Release(EnC_L);

Latch(EnC_H);
output_d(adH);
Release(EnC_H);
// delay_us(10);

output_low(CS);
output_low(WE);
output_d(Data);
output_high(WE);
output_high(CS);
}

int8 Read_61256(int16 address)
{
int8 data_read;

adH = make8(address,1);
adL = make8(address,0);
Latch(EnC_L);
output_d(adL);
Release(EnC_L);

Latch(EnC_H);
output_d(adH);
Release(EnC_H);

set_tris_d(0x00);
output_low(CS);
output_low(OE);
data_read = input_d();
output_high(OE);
output_high(CS);
return(data_read);
}

void main()
{

setup_adc_ports(NO_ANALOGS);
setup_adc(ADC_OFF);
setup_psp(PSP_DISABLED);
setup_spi(FALSE);
setup_wdt(WDT_OFF);
setup_timer_0(RTCC_INTERNAL);
setup_timer_1(T1_DISABLED);
setup_timer_2(T2_DIV_BY_16,20,16);
setup_timer_3(T3_DISABLED|T3_DIV_BY_1);
setup_oscillator(False);

release(EnC_L);
release(EnC_H);
output_high(OE);

printf("Starting...\r\n");
write_61256( 0x105, 'C' );
write_61256( 0x106, 'A' );
while(1)
{


data_out = read_61256( 0x105 );
printf("Address=0x105 char 'C' was written char=%C was read\r\n" , data_out);


data_out = read_61256( 0x106 );
printf("Address=0x106 char 'A' was written char=%C was read\r\n" , data_out);

delay_ms(100);

}
}

[Ttelmah]

The latch logic, appears wrong. If I remember right, the 373, is a transparent latch, with the output following the input, so long as the control input is high, and latching the input, when the signal drops. This is different from a 374, which is edge triggered on the rising edge of the control signal. Double check this logic.

Best Wishes

[vibrasys]

Hmm..
Here's what i had in mind for the write sequence:
- enable latch Low address
- place address adL on bus
- disable latch Low address
- enable latch High address
- place address adH on bus
- disable latch High address
- cs ram low
- wr ram low
- byte on ram i/o databus
- wr high
- cs high
And for the read sequence:
- enable latch Low address
- place address adL on bus
- disable latch Low address
- enable latch High address
- place address adH on bus
- disable latch High address
- port input mode
- cs ram low
- rd ram low
- read databus
- rd ram high
- cs ram high

you said "The latch logic, appears wrong." Can you suggest where i went wrong and how it should be?i've seen in the datasheet of pic18F8722,page 103 the use of transparent latch 373 for mem addressing.

Anyway thankx a lot Ttelmah for replyin'.....and go easy on a newbie dude ;)
regards

[vibrasys]

[Ttelmah]

Well done.
Sorry I didn't reply to the earlier 'come back', I was out. However the result was 'good' in the end. :-)

Best Wishes

[magestik]

Hello everybody,

I know this topic is quite old, but I am currently using a PIC16F84A with this CY62256LL Ram, I used vibrasys code, but I don't use any latch.

First problem, the code gives me nothing, I can't seem to be able to write or read to the chip.

Furthermore, I don't receive anything on my hyperterminal with the RS232, but the settings are good.

Could someone be of any assistance ? It would be greatly appreciated.
Thank you very much.

[ckielstra]

[magestik]

[ckielstra]

[magestik]

I've never delt with ram chip before. So the address is for where you want to write in the chip ? I thought it was THE address of the chip, like with I2C where you send the adress of the peripheral prior to data, here it would have been 0x00.
I get it now, the 15 bits of address need to be linked to the pic also.

I don't have the software here I can't tell you the version number for now.

For a simple program, i did try something like :

[dyeatman]

According to the data sheet you must have CE LOW, OE and WE HIGH.

Next set the desired address on the address lines, assert the data on
the I/O pins then pulse WE low to write the data to the selected address.

[magestik]

I'll try with that order tomorrow

But just the "printf" should print something on the hyperterminal. I just added a max232 to the serial output of the pic to display onto the computer. The baud rate and options are equal on both sides, yet nothing is printed :(.

[magestik]

Well i added some verification code :