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two hardware UARTs CCS support ? |
Posted: Tue Aug 11, 2009 10:36 pm |
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Hello everybody.
I have a question about two hardware uarts.
The PIC18F63J11 have two hardware uarts inside.
My CCS version is 4.084.
Could CCS support two hardware uart ?
My 18F63J11's PIN_C6 PIN_C7 can working at #int_RDA.
But PIN_G1 PIN_G2 can't work ... at #int_RDA2
Please help me. Thanks.
.C
Code: | #int_RDA
RDA_isr()
{
buff1 = getc(coma);
fprintf(coma,"%c",buff1);
}
#int_RDA2
RDA2_isr()
{
buff2 = getc(comb);
fprintf(comb,"%c",buff2);
}
void LEDHL()
{
output_high(pin_b0);
delay_ms(1000);
output_low(pin_b0);
delay_ms(1000);
}
void main()
{
setup_adc_ports(NO_ANALOGS|VSS_VDD);
setup_adc(ADC_OFF|ADC_TAD_MUL_0);
setup_psp(PSP_DISABLED);
setup_spi(SPI_SS_DISABLED);
setup_wdt(WDT_OFF);
setup_timer_0(RTCC_INTERNAL);
setup_timer_1(T1_DISABLED);
setup_timer_2(T2_DISABLED,0,1);
setup_timer_3(T3_DISABLED|T3_DIV_BY_1);
setup_comparator(NC_NC_NC_NC);
setup_vref(FALSE);
enable_interrupts(INT_RDA);
enable_interrupts(INT_RDA2);
enable_interrupts(GLOBAL);
for(;;)
{
LEDHL();
fprintf(coma,"Testing...."); <---- working now
delay_ms(500);
fprintf(comb,"Testing...."); <---- Can't work :sad:
delay_ms(500);
}
}
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.h
Code: |
#FUSES NOWDT //No Watch Dog Timer
#FUSES WDT128 //Watch Dog Timer uses 1:128 Postscale
#FUSES HS
#FUSES NODEBUG //No Debug mode for ICD
#FUSES NOXINST
#FUSES STVREN //Stack full/underflow will cause reset
#FUSES NOPROTECT //Code not protected from reading
#FUSES FCMEN //Fail-safe clock monitor enabled
#FUSES IESO //Internal External Switch Over mode enabled
#FUSES PRIMARY
#FUSES RESERVED //Used to set the reserved FUSE bits
#use delay(clock=20000000)
#use rs232(baud=115200,parity=N,xmit=PIN_C6,rcv=PIN_C7,bits=8,stream=coma)
#use rs232(baud=9600,parity=N,xmit=PIN_G1,rcv=PIN_G2,bits=8,stream=comb) |
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FvM
Joined: 27 Aug 2008 Posts: 2337 Location: Germany
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Posted: Wed Aug 12, 2009 7:13 am |
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Can't work in my opinion implies more than "doesn't work, but I don't know why". But you didn't tell a particularly observation.
I see, that V4.086 seems to access the correct SFRs for UART2. There may be a non-obvious bug with the built-in function code, of course. But your question can be answered clearly: CCS is supporting the second UART.
I didn't check with V4.084 and I don't have the chip to test if the SFR accesses are reaching the hardware.
I'm however under the impression, that PCH is setting a wrong baud rate value for the second UART. You may want to check the TX2 waveform with an oscilloscope and set the SPBRG2 register manually in your code, if you can verify this assumption. |
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