CCS C Software and Maintenance Offers
FAQFAQ   FAQForum Help   FAQOfficial CCS Support   SearchSearch  RegisterRegister 

ProfileProfile   Log in to check your private messagesLog in to check your private messages   Log inLog in 

CCS does not monitor this forum on a regular basis.

Please do not post bug reports on this forum. Send them to CCS Technical Support

Crystal frequency for PIC18F4550

 
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion
View previous topic :: View next topic  
Author Message
russk2txb



Joined: 30 Mar 2008
Posts: 109
Location: New Jersey

View user's profile Send private message

Crystal frequency for PIC18F4550
PostPosted: Mon Jul 12, 2010 10:06 am     Reply with quote

I'm looking for some advice on selecting the best crystal frequency. The Microchip data sheets give various configurations but there seems to be no suggestions why one would be used compared to another. For example, it appears that I can use a 48 MHz crystal and no divide for the PLL or MCU clock (in HS mode). Would that be best? Or is it better to use the 20 MHz crystal and use PLL / 5 and CPU / 2 in HSPLL mode? I guess the question boils down to, is it better to use PLL and a low frequency crystal?

Thanks, Russ
Ttelmah



Joined: 11 Mar 2010
Posts: 19549

View user's profile Send private message

PostPosted: Mon Jul 12, 2010 10:15 am     Reply with quote

You can't use a 48MHz crystal. Highest frequency supported by the oscillator circuitry, is 25MHz. Above 25MHz, you have to use an external _oscillator_, not just a crystal.
For 'fast' USB, you can use any mutliple of 4MHz, up to 24MHz.
The USB PLL, seems _slightly_ more reliable, when fed with a divided source, rather than directly from a crystal. So, 8MHz, 12Mhz, 16MHz, 20MHz, and 24MHz.
Generally, lower frequency crystals, reduce the risk of RF noise problems, however if the board is well designed, this is a minor.
Realistically choosing between these possible crystal values comes down to price/availability, possible duplication of stock if used in other projects, reducing the number of component lines needed, etc. etc..

Best Wishes
russk2txb



Joined: 30 Mar 2008
Posts: 109
Location: New Jersey

View user's profile Send private message

PostPosted: Mon Jul 12, 2010 2:26 pm     Reply with quote

Thanks Ttelmah. I was leaning towards the 20 MHz crystal anyway as that's what I used in another project. I did not see where it says that 25 MHz is the highest frequency crystal that can be used.

Thanks, again,
Russ
ckielstra



Joined: 18 Mar 2004
Posts: 3680
Location: The Netherlands

View user's profile Send private message

PostPosted: Mon Jul 12, 2010 4:41 pm     Reply with quote

russk2txb wrote:
I did not see where it says that 25 MHz is the highest frequency crystal that can be used.
It is in Table 28.8 of the datasheet: 'TABLE 28-8: EXTERNAL CLOCK TIMING REQUIREMENTS'
KnowMore



Joined: 05 Jul 2010
Posts: 9
Location: Vietnam

View user's profile Send private message

PostPosted: Wed Jul 14, 2010 12:37 am     Reply with quote

ckielstra wrote:
russk2txb wrote:
I did not see where it says that 25 MHz is the highest frequency crystal that can be used.
It is in Table 28.8 of the datasheet: 'TABLE 28-8: EXTERNAL CLOCK TIMING REQUIREMENTS'

I think we have something in wrong. It's no needed divide_by_12 before PLL if primary oscillator cannot run with above 25MHz crystal.
I've ever use both 48MHz and 40MHz crystal in HS mode, and didn't mind about any error Smile.

I think we should use Low-Frequency Crystal and PLL, more power-consumption but less noise.
_________________
GOOD TODAY IS ENEMY OF BETTER TOMORROW
Ttelmah



Joined: 11 Mar 2010
Posts: 19549

View user's profile Send private message

PostPosted: Wed Jul 14, 2010 4:07 am     Reply with quote

Don't confuse the internal oscillator, with the clock input.
If you look first at the table of crystals/oscillator configurations (2-3), you will see that the top three lines, using /10, /12, and no division att all (direct feed), are only listed for EC, ECIO, ECPLL, and ECPIO modes. These modes use an external _oscillator_. All the ones using 'HS', or 'HSPLL' (or XT), and the internal _oscillator_ block, are below 24MHz.
If you look at the table Ckielstra points you to, you will see that the clock is specified to run at 48MHz, but _not_ using a crystal.
If you have used it at this, you have been lucky. It is common for the oscillator to work well past spec, _but_ should not be relied on....

Best Wishes
KnowMore



Joined: 05 Jul 2010
Posts: 9
Location: Vietnam

View user's profile Send private message

PostPosted: Thu Jul 15, 2010 12:11 am     Reply with quote

Ttelmah wrote:
Don't confuse the internal oscillator, with the clock input.
If you look first at the table of crystals/oscillator configurations (2-3), you will see that the top three lines, using /10, /12, and no division att all (direct feed), are only listed for EC, ECIO, ECPLL, and ECPIO modes. These modes use an external _oscillator_. All the ones using 'HS', or 'HSPLL' (or XT), and the internal _oscillator_ block, are below 24MHz.
If you look at the table Ckielstra points you to, you will see that the clock is specified to run at 48MHz, but _not_ using a crystal.
If you have used it at this, you have been lucky. It is common for the oscillator to work well past spec, _but_ should not be relied on....

Best Wishes


I think you are right.
Thanks!
_________________
GOOD TODAY IS ENEMY OF BETTER TOMORROW
Display posts from previous:   
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion All times are GMT - 6 Hours
Page 1 of 1

 
Jump to:  
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum


Powered by phpBB © 2001, 2005 phpBB Group