Ttelmah
Joined: 11 Mar 2010 Posts: 19539
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Posted: Thu Jul 28, 2011 8:32 am |
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What individual examples will do, will be much better than the specified figures (which should be achievable by all chips, right across their operating voltage specs). The frequency limit for the CCP counter, is not '20MHz'. It is specified in the data sheet as an input period >:
(3Tcy+40)/N
where N is the prescaler used.
So with /16, and a chip at 20MHz (Tcy=50nSec), equals
(150+40)/16nSec = 11.875nSec, or 84MHz.
However there are also limits for the high time, and low time, at 20nSec each, with the prescaler, so 25MHz is the highest 'warranted'. Individual chips, at particular voltages, may well go far past this.
However realistically, why not just use an external hardware /10 divider?.....
Best Wishes |
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