dsPIC33 I2C timing issue 80 MHz

[egadget1]

I have a problem with a dsPIC33 running internal 7.37Mhz crystal feed to a PLL that runs the device at 80 MHz. The I2C device runs fine at 7.37 MHz. I think there is a setup problem when I run it at 80 MHz. I measured the setup time with an oscilloscope @ 7.37MHz and its 300ns, but when I measure it at 80MHz it only 80ns. I think the I2C spec says the setup should be 300ns. My device does not ACK after the address to the device is sent. Is there a register that I can write to to fix this or am I stuck at running it at 7.37 MHz? Thanks in advance

[FvM]

Please show some details, #use i2() and #use delay() statement and compiler version.

[egadget1]

Well I fixed it by adding a 100pf capacitor to the SCL line. Microchip need to add a register to add delay to I2C lines. When running these devices at 80 MHz there hardware does not account for the speed. I might just switch to bit banging in software the i2c instead of using the built in i2c hardware. For now it seems to be working with the capacitor.

Here is my #use i2c
#use i2c(MASTER,FAST=100000,SDA=PIN_B9,SCL=PIN_B8,FORCE_HW)

[Ttelmah]

300nSec, is _not_ required by the I2C spec for the falling edges of the drive gates. 80nSec, is fine. tF, at 300nSec, is the _maximum_ allowed on the bus for standard mode. tof is the gate switch low time, and again is only specified as a maximum, with no minimum required. (except for fast mode+).
The problem is that the faster the falling edges, the greater the risk of ringing on the bus. This is a second feature of Rs in I2C. You can increase Rs, within the limits that tf must not exceed 300nSec, and that the bus low level at the opposite ends of the bus must be OK, to help avoid the risk of ringing. I'd suggest you get rid of the capacitor, and try instead add series resistors to the bus. Perhaps 220R. These are often needed already when using fast mode drivers on standard mode busses, and I'd guess the Microchip drivers support fast mode+, making this even more of a problem.
The minimum allowed fall time for an Hs mode driver is 10nSec, into a bus capacitance between 10, and 100pF. Remember also that decreasing the Rp resistor values will generally slow the fall times.
Also look three times at your bus layout. This can massively affect ringing problems.

Best Wishes