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tonkostz
Joined: 07 May 2011
Posts: 40
Location: Bulgaria
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| Question about 3 PWM signals and interrupts |
 Posted: Sun Feb 10, 2013 2:38 am |
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I want to generate 3 PWM signals as shown in the figure below.
I'm trying to make it with this code with no success.
PWM_1 is ok but PWM_2 and PWM_3 are overlapping - PWM_3 starts before PWM_2 has ended.
Frequency will be between 7 and 38Hz. It's fixed for the example.
PWM_1 duty will vary from 150uS to 2mS and PWM_2 is fixed and will be 100uS max.
| Code: | #include <18f2431.h>
#fuses H4,NOWDT,PROTECT
#use delay(clock=40000000)
#define PWM_1 PIN_B2
#define PWM_2 PIN_B3
#define PWM_3 PIN_B4
#define LOOPCNT 3000
int8 width=50;
#INT_RTCC
void tick_interrupt(void)
{
static int16 loop = LOOPCNT;
static int8 pulse,pulse2,pulse3;
if(--loop == 0)
{
loop = LOOPCNT;
pulse = width;
pulse2 = 1;
pulse3 = pulse-pulse2;
}
if(pulse)
{
output_high(PWM_1);
pulse--;
}
else
{
output_low(PWM_1);
}
if(pulse2)
{
output_high(PWM_2);
pulse2--;
}
else
{
output_low(PWM_2);
if(pulse3)
{
output_high(PWM_3);
pulse3--;
}
else
{
output_low(PWM_3);
}
}
}
void main()
{
setup_timer_0(RTCC_INTERNAL | RTCC_DIV_1 | RTCC_8_BIT);
enable_interrupts(INT_RTCC);
enable_interrupts(GLOBAL);
while(true);
} |
[img][/img][img][/img] |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19546
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| Posted: Sun Feb 10, 2013 3:16 am |
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Seriously, consider doing this a very different way.....
As it stands, your processor will be interrupting every 256 instructions, even when the signals don't want to change. Given that it takes 60+ instructions to get into and out of an interrupt handler, and the counting/tests in the handler (quite a few instructions more), the processor is going to be spending most of it's time going into and out of the ISR.
Take advantage of the CCP's. If you are saying that the PWM-1, always rises at the start, and falls at the end, then, program CCP1, to reset it's output on a programmed count.
Start by raising PWM-1, and PWM-2. Have PWM-2 using the CCP1 pin. Program the time into CCP1, for the width required for PWM-2, and enable it's interrupt.
Then when CCP1 interrupts, PWM-2 will already have been dropped by the hardware. So now raise PWM-3 (use the CCP2 pin for this), and program into this the time required for PWM-3. Disable the CCP1 interrupt, and enable the CCP2 interrupt, and exit. The time taken to get into the interrupt handler will ensure that PWM-2 and PWM-3 don't overlap.
Then when CCP2 interrupts, PWM3 will have just dropped, so drop PWM-1.
Cycle finished. Now wait till the cycle is required again, and repeat.
Since the CCP's will be operating off Timer1, use this overflowing to start the cycle again. When it interrupts, load the new count at the start of the ISR (time for the cycle required), and set the CCP1 value, and start the CCP1 interrupt. Timer1 will want to be in 16bit mode.
Working this way, you will just have interrupts at each of the edges. Timer1 for the first edge, CCP1 for the second, CCP2 for the third, and back to Timer1 again.
Best Wishes |
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asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
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| Posted: Sun Feb 10, 2013 6:32 am |
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are "pwm 2 and pwm3"
basically the inverse of each other - carried along the time line -
or are both set to zero or one , at some point ?
Do U care to show multiple cycles of the long term waveform you hope to generate ? |
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tonkostz
Joined: 07 May 2011
Posts: 40
Location: Bulgaria
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| Posted: Sun Feb 10, 2013 10:23 am |
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The waveform shows only the pulse width of the three pwm signals without the pause between them. PWM_2+PWM_3=PWM_1.
PWM_2 and PWM_3 are inverse of each other but not with same pulse width. PWM_2 is fixed at 100uS and PWM_3 changes when PWM_1 changes - PWM_3=PWM_1-PWM_2. |
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Mike Walne
Joined: 19 Feb 2004
Posts: 1785
Location: Boston Spa UK
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| Posted: Sun Feb 10, 2013 10:59 am |
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Clarify EXACTLY what you want.
At this stage it's certainly not clear to me.
Show us CLEAR diagrams of ALL the variations required.
Otherwise both you and the rest of us are wasting our time.
Mike |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19546
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| Posted: Sun Feb 10, 2013 11:36 am |
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The obvious thing then is to generate PWM-3 in hardware.
PWM-3 = PWM-1 & (! PWM-2)
One logic chip (you can do it with a quad nand).
Use the CCP's to time PWM-1 and PWM-2.
Best Wishes |
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tonkostz
Joined: 07 May 2011
Posts: 40
Location: Bulgaria
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| Posted: Sun Feb 10, 2013 12:09 pm |
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Variable frequency from 7Hz to 38Hz and variable pulse width from 150uS to 2mS. Here is a picture.
 |
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asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
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| Posted: Sun Feb 10, 2013 1:49 pm |
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what is this set of waveforms supposed to DO/ control/trigger ?
BUT PWM_2 looks like a great candidate to be produced by a 74hc221, triggered by rising pwm_1 ( and potentially fed back to an input of the pic )
that then only leaves the linkage between pwm_1 and 3 to consider |
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tonkostz
Joined: 07 May 2011
Posts: 40
Location: Bulgaria
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| Posted: Tue Feb 12, 2013 11:46 am |
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| Common Rail electromagnetic injectors. |
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asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
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| Posted: Tue Feb 12, 2013 1:44 pm |
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as in solenoid , hydraulic valve actuators ??
or some technology ?
what do each of the delays represent ?
( repetition frequency, force OPEN, drive CLOSED? ) ??
are they locked to some other timing aspect of the system you have not revealed yet ? |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19546
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| Posted: Tue Feb 12, 2013 3:18 pm |
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Electromagnetic, suggests solenoid injectors. As far as I know, only Piezo, and solenoid injectors are used on this type of system.
Best Wishes |
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asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
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| Posted: Tue Feb 12, 2013 4:31 pm |
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if your timing diagram is correct and time aligned , all you have to do is create PWM1 signal in the pic.
THEN discrete HC logic - can do the rest perfectly.
-----------------
PWM 2 can be generated by a precision one shot multivibrator IC as i mentioned for a constant 100us when triggered
------------------
PWM3 can be created by using the FALLING edge of pwm2 to set a LATCH
such as 74hc74
------------------
the HC74 is in turn reset/ Cleared by the falling edge of PWM1 and you have a complete cycle properly locked. |
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