Set PWM Configuration

[SeeCwriter]

Are there built-in functions to configure the Enhanced PWM for different output configurations (single, half-bridge, full-bridge, etc.) and dead-band delay? There are no options for this in the #use pwm statement and I'm not seeing any functions in the May 2014 compiler manual.

I'm using a PIC18F8722, and PCHW v5.035.

[PCM programmer]

From looking at the .LST file, it looks like this should work:
The deadband is specified as the 2nd parameter (after the comma)
in the setup_ccp1() statement:

[SeeCwriter]

Ok, I'm blind. It's plain as day. Thanks.

[SeeCwriter]

Why would I get an "Undefined identifier" error for CCP_DELAY in the following statement?

setup_ccp1(CCP_PWM | CCP_PWM_HALF_BRIDGE | CCP_SHUTDOWN_AC_L | CCP_SHUTDOWN_BD_L | CCP_DELAY);

The manual clearly shows it as one of the options. And the 18F8722 has the feature.

[PCM programmer]

Well, the manual is wrong. I figured out what apparently does work.
If you want a clarification, you should send an email to CCS support.

[Ttelmah]

Also, look at the chip errata.

CCS left it out for a reason..... :(

You should be able to use it by creating your own define, but they you'll have to be super careful about the duty cycles you use. (0-3 not allowed, and 7, 11, 15, 19 etc..). Ouch.

[SeeCwriter]

I asked tech support about it, and the response was, "not all options are available on all devices. Check the device header file." So I did a grep of the entire Devices directory. Not a single device header file contains a define for CCP_DELAY. So it appears that CCS just doesn't support that feature, period.

I don't understand your comment about being careful with duty cycles, and why certain numbers are not allowed.

[Ttelmah]

Several chips do happily let you use deadband's, but on your's there is an erratum:
"35. Module: ECCP (PWM Mode)
When configured for half-bridge operation with
dead band (CCPxCON<7:6> = 10), the PWM output
may be corrupted for certain values of the
PWM duty cycle. This can occur when these
additional criteria are also met:
• a non-zero, dead-band delay is specified
(PxDC6:PxDC0 > 0); and
• the duty cycle has a value of 0 through 3, or
4n + 3 (n ≥ 1).
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices."

So if you enable the dead-band in half bridge, instead of getting the nice 'no clash during crossover' behaviour, you may get corrupted PWM outputs. Uurgh.....

[SeeCwriter]

Interesting. Since that errata was released in 2006, and it applies only to Rev A1 silicon, you don't think this has been fixed by now?
The errata sheet for the Rev B1 silicon, released in 2009, has a different CCP module issue that affects modules I'm not using in my application.
I would think they are only shipping Rev B1, or later, silicon, now.