DAC Module does not work in dspic33fj128gp804

[AlPicCss73]

Hi guys!

I'm trying to use the internal dac modules in the 33fj128gp804. but they're not working and I have no idea about that. in the following topic the same chip is used and seems working at all.
http://www.ccsinfo.com/forum/viewtopic.php?t=45621&highlight=dspic33fj128gp+dac
The problem that I'm facing is when I configure the DAC module its output is constant and does not change anyway. I disable and enable the midpoint but it's still there and the negative and the positive outputs are at 1.5 and 1.7 volt respectively. In mean time I don't find any problem with my hardware at all.
This is my code:

[jeremiah]

We used a built in dac on another chip (A PIC24 I think) and on ours using the default settings we had to continuously reload the DAC value using its interrupt. Otherwise it would release the line and not output the value we wanted.

We ended up moving to an external DAC later on for other reasons, so I don't know if we could have configured it differently or not, but it might be something you could try to see if it is the same scenario. To get a specific value we would use a global variable to hold the value and then have the interrupt use that variable to reload the register each time it fired.

We didn't spend enough time on it to see if we were doing the hardware wrong or if the configuration was wrong though.

It was something like:

[AlPicCss73]

Thanks, But nothing changed!
As I understand, using an infinite loop do the same thing like your code. It's really confusing for me that why negative and positive outputs both have high values. it's really disappointing that I don't find any clue.

[Ttelmah]

The first thing is that you are going to be sending the values too fast. 100Ksps max with a 25.6MHz master DAC clock.
Then what is your DAC clock rate?. You are setting the divisor to 1, the maximum rate for this is 25.6MHz.

Understand this is not a conventional DAC. It is designed for audio synthesis. It has a master clock, which it needs. If you look at the example post you have found, he gives how he is calculating this, and sets it up. He then tests the DAC register for empty (or you can use the interrupt for this), and loads the next value. It synthesises points 'between' the values you give, for 256 DAC clocks between each load.

If you don't reload the register, the output will fade to zero over the next 256 cycles (this is what Jeremiah was seeing).

[AlPicCss73]

Thanks, but nope! that's not the case as I know the internal clock is about 1/256 of external clock, so with my 8MHz clock this won't be a problem. In spite of this fact, I used the slowest mode and nothing changed. It's reluctant to any changes and that's a strange thing.

[Ttelmah]

No.

There are two different DAC rates. The master clock, which is directly 'at' the clock rate you set it, and DAC 're-sample' rate, which is at 1/256th this.

What happens is that the DAC outputs a value at every cycle of it's master clock (the Aux clock). It is this that is limited to 25.6 MHz. Every 256 of these, it requests a new value (INT_DAC, or the buffer empty bit). This then gives the DAC 'update' rate. So you have a DAC update rate limited to 100KHz, and a DAC master clock limited to 25.6MHz (256 times the update rate). The values it outputs in the 256 cycles are generated by hardware interpolation. This is the 256* 'oversampling' supported by this DAC.

Now the DAC, can be fed from it's own external crystal on the secondary oscillator, or from the system clock. Which are you selecting?. This is the SELACK bit. What speed are you running the system?.

If you look at the example you refer to, he is using the 7.37MHz FRC oscillator, and clocking the CPU at 16* this to give 117.92Mhz. He then divides this by 8, to give an Aux clock (he calculates) of 22.115Mhz. So under the 25.6MHz limit. This then potentially gives a DAC update rate of 86.4 KHz.
If you look though, this figure is wrong (117.92/8 = 14.74MHz). His update rate will then be 57.5KHz.

So though he is working off just 7.37MHz, he is clocking the DAC at 14MHz. The clocking needs to be got right, before you have any hope of getting the chip to update correctly.

[Ttelmah]

[jeremiah]

No disagreement here. Unfortunately I don't get to make those kind of decisions where I work. Luckily we had another reason to switch (I forget what is was now...like 2 or 3 years ago).

[Ttelmah]

As a further comment to the original poster, this DAC, takes a signed value, so for 'zero', the output will be sitting at half the reference voltage....

[AlPicCss73]

Thanks guys! Really useful comments.
But I'm still confused, sort of! And that's because I've never changed the clock settings except those configuration registers. Would you help me in setting the registers?
I'm using an 8MHz external crystal and I want at least meet the minimum requirements to bring it to the life. My configuration registers are:

[Ttelmah]

You keep telling us you are using an 8MHz crystal, but not how fast you are clocking the PIC?.

Post your fuses, and your clock setup line.

The crystal on these PIC's does not tell you how fast the chip is going.

Unless you mean you have this on the secondary oscillator?.

[AlPicCss73]

You're right! But that's because I just wanted to run it anyway. I used the basic settings, using external crystal without PLL which results in 4Mips and don't use any secondary oscillator. All configuration bits are here:

[Ttelmah]

What I am looking for, is a _basic_ program showing what you are trying to do, with the CCS code. So something like: