PCM programmer
Joined: 06 Sep 2003
Posts: 21708
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 Posted: Mon Jan 05, 2004 2:42 am |
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| Quote: | Regarding the clock line for this eeprom, I constantly see that low level
routines TRISTATE to high impedance when bringing this line high. |
This allows "clock stretching" by the slave device. This is possible
because the Master does not drive the SCL line high, but instead
it is brought high by a pull-up resistor.
From the i2c spec:
"On the byte level, a device may be able to receive bytes of
data at a fast rate, but needs more time to store a received
byte or prepare another byte to be transmitted. Slaves can
then hold the SCL line LOW after reception and
acknowledgment of a byte to force the master into a wait
state until the slave is ready for the next byte transfer in a
type of handshake procedure".
Here's the CCS code after the (software i2c) Master has transmitted
a byte to the slave device.
0023 BCF 06.1
0024 BSF 03.5 // Bank 1
0025 BCF 06.1
0026 NOP
0027 BSF 06.0
0028 NOP
0029 NOP
002A BSF 06.1 // Set SCL as an input pin
// Here's the loop where they test for clock stretching by the slave.
002B BCF 03.5 // Bank 0
002C BTFSC 06.1 // Test SCL pin. Skip next ins. if it = 0
002D GOTO 030 // If SCL = 0, exit this loop
002E BSF 03.5 // Bank 1
002F GOTO 02B // Jump back to the start of the test loop
0030 ... |
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