ADC Frequency and TAD

[Tom-H-PIC]

I'm using an 18F2553.
Crystal 20Mhz
Fuses set for 48Mhz for USB.

Can someone explain to me the correlation between the TAD setting and the ADC frequency?
I’m just trying to figure out the total acquisition time for 12 bits.
Also need to understand how changing TAD and the frequency selection will change that.
I would also like to understand how to calculate the sample per second.
Thank you all.
Tom

[Ttelmah]

The ADC, takes 13 cycles of it's internal clock, to perform a 12bit conversion.

This internal clock, is 'Tad'. It has a specified maximum frequency of 1.25MHz.

The ADC circuit itself, is seen electrically, as a capacitor inside the chip, with a series resistor to the external pin. When a 'reading' is actually performed, the capacitor is disconnected from the pin. Also, if the ADC samples another channel, the capacitor is connected to this pin, instead of the one being read. Hence, when you first connect to a signal, or between readings on a signal, there is a minimum tme needed for the capacitor to charge to get close to the incoming voltage. This is Tacq. It is specified for your chip, at fractionally under 3uSec, for an analog source wth an impedance of 2.5KR _or lower_. This is basically the 'worst case' time, assuming the capacitor is charged to 0v, then attached to a source at the full ADC reference voltage, for the capacitor to charge to withing half a bit voltage of the real value (and therefore start giving the correct reading).

So the total sequence needed, to read a channel, from a standing start, is:

Select channel
Allow capacitor to charge for Tacq
Take the reading (13*Tad).

Now, on the older PIC's, you had to manually provide the Tacq delay. However on the more modern chips,the ADC itself, can automatically provide the delay, programmable in eight steps, up to 20 Tad.

So, if you start with a clock rate of 48MHz, the fastest legal AD clock, is given by Fosc/64 = 750000Hz.

Now, this gives Tad=1.33uSec.

If using the hardware Tacq delays, the lowest one to give reliable acquisition, is then 4*Tad.

The total time to acquire and take a reading, then become (13+4)*Tad = 22.66uSec.

You can take a reading _fractionally_ faster, by not using the Tacq delay, and instead adding a manual 'delay_us(3)'. This then gives a total time of:

13*Tad+3uSec = 20.33uSec

It is also worth realising that you can actually get faster conversion, by reducing the processor clock. Selecting a master clock of 1.25MHz*32 = 40MHz, allows Tad to actually be selected to it's minimum value, giving the a total time then of:
Tad=0.8uSec

17*Tad= 13.6uSec

This is a 'classic' example of how chosing a clock carefully, can at times give unexpected improvements.

Best Wishes

[Tom-H-PIC]

Ttelmah Thank you so much!
I think that I'm understanding now.
Just one or two questions.

[srikrishna]

Hello , I have searched the same in the internet It says

[Ttelmah]

Yes. But.....

The ADC is what is known as a 'successive approximation' type. In then the chip internally has a DAC and a comparator. It outputs the most significant bit (512) to the DAC, and sees if the incoming voltage is above or below this. If above this bit is left turned on, if below this bit is turned off. It then tries the next bit and does the same thing. So to do a conversion it has to do a series of outputs, one for each bit. These steps each take Tad.
However it has to do other things. The voltage must not change during the conversion. So there is a 'sample and hold' circuit to ensure the voltage remains stable. So before the first output, the chip has to enable the sample and hold, then disconnect the actual input. Then perform the tests, and then transfer the result from the latch used for the tests, into the ADC output register. Each of these extra steps also uses a Tad clock. So the 10 bit conversion takes 13 clocks.

[srikrishna]

HI!! I Can't understand the calculation of the following picture


https://www.teachmemicro.com/pic-microcontroller-tutorials/pic-adc/
A/c to my calculation it is something like that,
FOR FOSC/32

[Ttelmah]

Tad must not be _less_ than 1.6uSec (you don't tell us the chip, so we have to assume you are reading this right).

For the Fosc/2, it is (0.5uSec). Tad is the first line in the calculation, not the second (which gives the total time to perform the conversion, _not_ Tad...

The data sheet will have a table showing the recommended values. Beware that having a Tad very much greater than the minimum will eventually degrade the accuracy, as the sample and hold cannot hold forever....

[srikrishna]

Thanks