SPI-Problem send multiple bytes

[Sterngleiter]

Hello,
I would like to send 3 bytes via SPI, first and second Byte for the addressing and the third for data. However, I need answer from slave. I know that I can send one byte and have then one byte as answer. Somehow it does not work. When I rewrite my code just one byte I also get a byte. I have to send 3 bytes and possibly also receive 3. Can you tell me where I make a mistake.

Code Master:

[Ttelmah]

You should be loading your reply in the int_ssp. When this triggers the first time, load the reply you expect to receive for the second transfer.

Also you need to allow time. Problem is int_ssp triggers after the byte has transferred. Your slave needs to load the reply _before_ the master does the next transfer. You don't show your clock rates, but it will take typically about 40 instruction times before the slave can load the reply byte, so the master needs to pause for at least this long before issuing the second (and later) transfers.

[Sterngleiter]

8mhz internal clock is used. I have a waiting loop installed in master 5us after each send. How do I calculate something like that? do you have any suggestions for a program?

[Ttelmah]

At 8MHz you are executing 2MIPS. 40 instructions is then 20uSec. You need a little more than this (30uSec), and that only if you load the bytes inside the interrupt. In your code, you don't, you have to get out of the interrupt and read/match the data bytes, which will take several times as long....
Also you don't have any delay after sending the header byte.
Just have a counter, reset by the header byte, and incremented each time the interrupt is called after this, and load the byte based on this counter.

[Sterngleiter]

How would you solve the problem? I also have to work outside of interrupt.

[Ttelmah]

[Sterngleiter]

output_low(pin_c2);
spi_xfer(0x01);
delay_us(50);
eingang0=spi_xfer(0);
delay_us(50);
spi_xfer(0x02);
eingang1=spi_xfer(0);
delay_us(50);
spi_Xfer(0x03);
eingang2=spi_xfer(0);
output_high(pin_c2);

I thank you very much for the approach. With master code are the delay right?
Between first send and receive you have a delay, not between the others. that's wanted, right?

[Ttelmah]

That's why it says //master.

I cut and pasted from your code. Added one extra delay on the first pair of transfers but missed one of the later pairs. Every pair of transfers need a delay between sending one byte and receiving the next.

[Sterngleiter]

Thanks, I will try tomorrow. Can we write if I have any questions?

[Ttelmah]

Yes, there are several people here who can help.

[Ttelmah]

Looking at it I realise you are missing one fundamental 'point' about SPI.

_Every_ SPI transaction, sends and receives a byte at the same time. You don't want to be clocking extra bytes out to receive the bytes back, use the transfers that are sending the bytes. So:

[Sterngleiter]

Code:

//master

PostPosted: Mon Sep 24, 2018 5:16 pm Post subject:
output_low(pin_c2);
spi_xfer(0x01); //single 'send only' transfer to signal start
delay_us(50);
eingang0=spi_xfer(1); //Now each send clocks back a reply
delay_us(50);
eingang1=spi_xfer(2);
delay_us(50);
eingang2=spi_xfer(3);
output_high(pin_c2);

I do not understand red marked. I send 2 times the 1 in the int_ssp but I set x = 0 When temp==1. it will not be overwritten

[Sterngleiter]

short question, why can not I simulate proteus spi. send runs but does not receive. the same code runs in the pic real time but not at proteus

[temtronic]

short answer
Proteus is busted ! Has been for YEARS, please read PIC101 sticky.

[Ttelmah]

Reason is the mode numbers are wrong. The SPI at both ends needs to have the same mode setting. Currently the slave has a different mode to the master resulting in it losing a bit of the transfer....