difference between Global Interrupt Enable bit

[srikrishna]

Hi guys! What is the difference between Global Interrupt Enable and Peripheral Interrupt Enable bit in pic 18f micro controller? What is their function?

[Ttelmah]

Read the chip data sheet.

The GIE (global interrupt enable) allows all enabled interrupts to start
responding.
The individual interrupt enables control each separate interrupt.
An interrupt handler is called when:
1) The GIE is TRUE.
2) The individual PIE is TRUE.
and 3) The physical interrupt flag is set.

[srikrishna]

What is unmasked interrupt ?

[temtronic]

All peripherals that can cause an interrupt have a 'control' bit in a register to enable or disable that feature. If set to a '0' that peripheral will not generate an interrupt, If set to a '1' it will generate an interrupt IF both 'peripheral' interrupt AND global interrupt bits are set.
The 'mask' is a way to enable/disable entire sets or groups of interrupts based upon what your program is supposed to do.

[srikrishna]

[Ttelmah]

Enables all interrupts that are not masked off by their PIE bits.

The bits are all 'masks'. The GIE, is a mask for all the interrupts.
The PIE bits mask each individual interrupt.

[temtronic]

There are several registers that are used depending on which PIC you have.
Generally speaking 'CONtrol' registers decide what to do, 'PIE' registers control 'enable' bits for peripheral device.
You need to read the datasheet of whatever PIC you're using as not all PICs have all peripherals !

[srikrishna]

[srikrishna]

I have read the datasheet of pic 18f2550. I guess INTCON, INTCON2 and INTCON3 controls the peripherals interrupt. PIR1,PIR2 registers contain the individual flag bits for the peripheral interrupts. PIE1, PIE2 registers contain the individual enable bits for the peripheral interrupts.

[Ttelmah]

No.
The INTCON registers contain GIE, then some of the physical interrupt flags
(though you don't need these when using an interrupt, they can be 'polled',
and they have to be cleared when the interrupt is exited (the compiler
does this for you unless you say otherwise). They also contain some 'P' bits
for some interrupts that sets the priority if interrupt priorities are enabled.
Have a look at this thread which discusses priorities:
<http://www.ccsinfo.com/forum/viewtopic.php?t=58480>

It is quite confusing, since they put a few of the priority bits here, and
the rest in the IPR registers.

The enables are then in the PIE registers, and the rest of the interrupt
flags in the PIR registers.

It suffers a little because as chips have grown areas that originally
contained things are no longer large enough, so new registers were
created, but to retain the reverse compatibility the old locations are
used for the older peripherals.

Key is that everything is described in the data sheet. If (for example), you
search for PIR1, you get basic layouts showing where it is and the bit
names, but then later in the sheet you get a whole page describing
every bit in the register.