IOC Port E DsPIC33CH512MP508

[dyeatman]

PCWHD 5.107
After hours of searching I am unable to find compiler support for IOC for Ports
D&E and I am looking at having to access the CNSTYLE/CNEN1/CNEN0 bits
directly. Anyone see something I am missing other than INT_Default?
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[jeremiah]

There's no #INT_CNI or enable_interrupts() options? all of my dspics have those normally.

edit: I usually have:

[dyeatman]

Thank you Jeremiah, I found CNIE but could not make it work so I figured
I was interpreting the name wrong. BTW, how did you set up the (neg/pos)
edge triggering? The edge setting options don't seem to support this.

I can make it work by defining and setting the registers directly but I prefer
using the CCS options if possible. With your confirmation I'll play with it some
more.
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[jeremiah]

Most of the chip drivers that support it have other enable_interrupts() options. One of my chips (not the same as yours) has

[Ttelmah]

Several parts:

On this particular chip, there are separate interrupts for each port.
So CNIA, CNIB, CNIC, CNID & CNIE.
Then on the DsPIC's, interrupt on change needs several registers to
setup. You can specify whether the interrupt is triggered by level, or
by the edge. This is controlled by the CNSTYLE bit, and the contents
of CNEN1x and CNEN0x. Which pin has triggered is in the CNFx register
for each port.
There are five registers for each pin on these chips. I think CCS gave
up on trying to set all of these, so leave it to you to do the configuration
of these. They offer the enable for the pins as Jeremiah shows, but not
control of whether this handles edges or levels. They default to just
handling levels setting the CNEN0X bits, and the master enable. Detection
of the bits in the flag register is left up to you.
Set them up as Jeremiah shows in his first post, using the CNIE
interrupt (for your port E), and then should work. However you have
to manually read/clear the CNFE register.

[dyeatman]

Thanks to both of you! With your help I now have a hybrid of CCS functions
and direct register accesses but it works. Hopefully they will get this cleaned
up more later.
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[Ttelmah]

Point the lack out to them.
This particular chip family is unusual in supporting the extra edge detect
option, and having separate IOC's on each port. I think the person writing
this originally at CCS put in the parts that the functions used on the other
chips had, but didn't get involved in adding support for this chip's 'extras'.

[jeremiah]