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Ken Johnson
Joined: 23 Mar 2006
Posts: 197
Location: Lewisburg, WV
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 Posted: Fri Feb 22, 2008 8:03 am |
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I would get the latest compiler version !
Ken |
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andredurao
Joined: 24 Apr 2006
Posts: 15
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| trying one more time |
| Posted: Thu Feb 28, 2008 7:32 am |
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Hi once again I'm here asking for help =)
now I've changed my code accord "Chipedit.exe" tool
and configured QEICON again,
the code it's working at the same way BUT I've noticed one thing really
strange, I connect PIN QEA and PIN QEB together and when I pulse (+vdd)
at both pins in parallel I can see that POSCNT decreases the value
but I still can't count position, when I turn the encoder on in QEA and QEB it counts 0 to 1 all the time....
should I use a flip-flop at the encoder and the output at qea qeb? datasheet doesn't say nothing about it, just about using Quadrature Encoders that's what I'm trying
| Code: |
#include "D:\pic\encoder\enc.h"
#include <LCD.C>
//configuracoes QEI
#byte QEICON = 0xFB6
#bit QEICONPDEC0 = QEICON.0
#bit QEICONPDEC1 = QEICON.1
#bit QEICONQEIM0 = QEICON.2
#bit QEICONQEIM1 = QEICON.3
#bit QEICONQEIM2 = QEICON.4
#bit QEICONUPDOWN = QEICON.5
#bit QEICONERROR = QEICON.6
#bit QEICONVELM = QEICON.7
#byte PR5H = 0xF91
#byte PR5L = 0xF90
#byte CAP1BUFH = 0xF69
#byte VELRH = 0xF69
#byte CAP1BUFH = 0xF68
#byte VELRL = 0xF68
#byte CAP2BUFH = 0xF67
#byte POSCNTH = 0xF67
#byte CAP2BUFL = 0xF66
#byte POSCNTL = 0xF66
#byte MAXCNTH = 0xF65
#byte CAP3BUFH = 0xF65
#byte MAXCNTL = 0xF64
#byte CAP3BUFL = 0xF64
#byte CAP1CON = 0xF63
#bit CAP1CONCAP1M0 = CAP1CON.0
#bit CAP1CONCAP1M1 = CAP1CON.1
#bit CAP1CONCAP1M2 = CAP1CON.2
#bit CAP1CONCAP1M3 = CAP1CON.3
#bit CAP1CONCAP1REN = CAP1CON.6
#byte CAP2CON = 0xF62
#bit CAP2CONCAP2M0 = CAP2CON.0
#bit CAP2CONCAP2M1 = CAP2CON.1
#bit CAP2CONCAPM2M2 = CAP2CON.2
#bit CAP2CONCAP2M3 = CAP2CON.3
#bit CAP2CONCAP2REN = CAP2CON.6
#byte CAP3CON = 0xF61
#bit CAP3CONCAP3M0 = CAP3CON.0
#bit CAP3CONCAP3M1 = CAP3CON.1
#bit CAP3CONCAP3M2 = CAP3CON.2
#bit CAP3CONCAP3M3 = CAP3CON.3
#bit CAP3CONCAP3REN = CAP3CON.6
#byte DFLTCON = 0xF60
#bit DFLTCONFLTCK1 = DFLTCON.1
#bit DFLTCONFLTCK2 = DFLTCON.2
#bit DFLTCONFLT1EN = DFLTCON.3
#bit DFLTCONFLT2SEN = DFLTCON.4
#bit DFLTCONFLT3EN = DFLTCON.5
#bit DFLTCONFLT4EN = DFLTCON.6
int16 qeicnt;
int16 drcnt;
#int_IC3DR
void IC3DR_isr(void)
{
drcnt++;
}
#int_IC2QEI
void IC2QEI_isr(void)
{
qeicnt++;
}
void main()
{
setup_adc_ports(NO_ANALOGS|VSS_VDD);
setup_adc(ADC_OFF|ADC_TAD_MUL_0|ADC_WHEN_INT0|ADC_INT_EVERY_OTHER);
setup_spi(SPI_SS_DISABLED);
setup_wdt(WDT_OFF);
setup_timer_0(RTCC_INTERNAL);
setup_timer_1(T1_DISABLED);
setup_timer_2(T2_DISABLED,0,1);
lcd_init();
enable_interrupts(INT_IC2QEI);
enable_interrupts(INT_IC3DR);
enable_interrupts(GLOBAL);
setup_oscillator(false);
QEICONPDEC0=0;
QEICONPDEC1=0;
QEICONQEIM0=0;
QEICONQEIM1=1;
QEICONQEIM2=1;
//bit 5 é somente de leitura
QEICONERROR=0;
QEICONVELM=1;
POSCNTH=0;
POSCNTL=0;
MAXCNTL=0xFF;
MAXCNTH=0xFF;
while(1){
printf(lcd_putc,"\f%03u-%03u %03u-%03u\n%05Lu d:%05Lu[%1u]",
POSCNTH,POSCNTL, MAXCNTL, MAXCNTH, qeicnt, drcnt, QEICONUPDOWN);
delay_ms(50);
}
}
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| Code: |
#include <18F4431.h>
#device adc=8
#FUSES NOWDT //No Watch Dog Timer
#FUSES WDT128 //Watch Dog Timer uses 1:128 Postscale
#FUSES HS
#FUSES NOPROTECT //Code not protected from reading
#FUSES IESO //Internal External Switch Over mode enabled
#FUSES BROWNOUT //Reset when brownout detected
#FUSES BORV27 //Brownout reset at 2.7V
#FUSES PUT //No Power Up Timer
#FUSES NOCPD //No EE protection
#FUSES STVREN //Stack full/underflow will cause reset
#FUSES NODEBUG //No Debug mode for ICD
#FUSES NOLVP //low voltage prgming, B3(PIC16) or B5(PIC18) used for I/O
#FUSES NOWRT //Program memory not write protected
#FUSES NOWRTD //Data EEPROM not write protected
#FUSES FCMEN //Fail-safe clock monitor enabled
#FUSES NOWINEN //WDT Timer Window Disabled
#FUSES T1LOWPOWER //Timer1 low power operation when in sleep
#FUSES HPOL_HIGH //High-Side Transistors Polarity is Active-High (PWM 1,3,5 and 7)
#FUSES NOWRTC //configuration not registers write protected
#FUSES NOWRTB //Boot block not write protected
#FUSES NOEBTR //Memory not protected from table reads
#FUSES NOEBTRB //Boot block not protected from table reads
#FUSES NOCPB //No Boot Block code protection
#FUSES LPOL_HIGH //Low-Side Transistors Polarity is Active-High (PWM 0,2,4 and 6)
#FUSES PWMPIN //PWM outputs disabled upon Reset
#FUSES MCLR //Master Clear pin enabled
#FUSES FLTAC1 //FLTA input is multiplexed with RC1
#FUSES SSP_RC //SCK/SCL=RC5, SDA/SDI=RC4, SDO=RC7
#FUSES PWM4B5 //PWM4 output is multiplexed on RB5
#FUSES EXCLKC3 //TMR0/T5CKI external clock input is muliplexed with RC3
#use delay(clock=20000000)
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